reset.vhd

来自「用QUARTUS编译通过的等精度频率计」· VHDL 代码 · 共 42 行

--/* RESET．VHD*/--复位模块
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity reset is
    Port (clk,rst:in std_logic;
	    cl,clr:out std_logic );
end reset;

architecture Behavioral of reset is

begin
process(clk,rst)
variable cnt:integer range 0 to 32000000;
begin
	if rst='0' then 
		cnt:=0;clr<='1';cl<='0';
	elsif rising_edge(clk) then
		cnt:=cnt+1;
		if cnt=1000000 then 	--cnt=1000000
			clr<='1';
		elsif cnt=2000000 then --cnt=2000000
			clr<='0';
		elsif cnt=3000000 then --cnt=3000000
			cl<='1';
		elsif cnt=19000000 then --cnt=19000000
			cl<='0';
		elsif cnt=20000000 then  --cnt=20000000
			cnt:=0;
		end if;
	end if;
end process;

end Behavioral;