cacodegen_tb.v

这是GPS接收机

`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:   13:41:24 04/06/2006
// Design Name:   CACodeGen
// Module Name:   CACodeGen_tb.v
// Project Name:  single_channel_p
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: CACodeGen
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////

module CACodeGen_tb_v;

	// Inputs
	reg clk;
	reg reset;
	reg [31:0] phase_cw;
	reg [31:0] freq_cw;
	reg [10:0] chip_cw;
	reg [31:0] data_in;
	reg [4:0] wr_addr;
	reg code_tab_wr;
	reg [11:0] cyc_cw;
	reg [18:0] zcnt_cw;

	// Outputs
	wire e_code;
	wire p_code;
	wire l_code;
	wire [31:0] data_out;
	wire clr;
	wire [11:0] cycles;
	wire [9:0] chips;
	wire [18:0] Z_cnt;

	// Instantiate the Unit Under Test (UUT)
	CACodeGen uut (
		.clk(clk), 
		.reset(reset), 
		.phase_cw(phase_cw), 
		.freq_cw(freq_cw), 
		.chip_cw(chip_cw), 
		.e_code(e_code), 
		.p_code(p_code), 
		.l_code(l_code), 
		.data_in(data_in), 
		.data_out(data_out), 
		.wr_addr(wr_addr), 
		.code_tab_wr(code_tab_wr), 
		.clr(clr), 
		.cycles(cycles), 
		.chips(chips), 
		.Z_cnt(Z_cnt), 
		.cyc_cw(cyc_cw), 
		.zcnt_cw(zcnt_cw)
	);

	initial begin
		// Initialize Inputs
		clk = 0;
		reset = 0;
		phase_cw = 0;
		freq_cw = 141733919;
		chip_cw = 0;
		data_in = 0;
		wr_addr = 0;
		code_tab_wr = 0;
		cyc_cw = 0;
		zcnt_cw = 0;

		// Wait 100 ns for global reset to finish
		#100;
        reset = 1;
		// Add stimulus here

	end
always #6.314 clk = ~clk;
endmodule