it51_core.v
来自「流片过的risc_8051源代码 verilog语言描述的~」· Verilog 代码 · 共 2,022 行 · 第 1/5 页
V
2,022 行
end
if (~Ready)
begin
Int_AddrA = Int_AddrA_r ;
Mem_A_Rd = 1'b1 ;
end
end
// Int_AddrA_r
always @(posedge Clk or negedge Rst_n)
begin
if (Rst_n == 1'b0)
begin
Int_AddrA_r <= {8{1'b0}} ;
end
else
begin
Int_AddrA_r <= Int_AddrA ;
end
end
//--------------------------------------------------------------------------
// PSW
assign PSW0 = ACC[7] ^ ACC[6] ^ ACC[5] ^ ACC[4] ^ ACC[3] ^ ACC[2] ^ ACC[1] ^ ACC[0] ;
assign Next_PSW7 = (SFR_Wr_i == 1'b1 & Int_AddrA_r == 8'b11010000) ? Res_Bus[7] : ((Status_Wr[7]) == 1'b1) ? Status_D[7] : PSW[7] ;
assign Next_ACC_Z = (ACC_Q == 8'b00000000 & ACC_Wr == 1'b1) ? 1'b1 : (ACC == 8'b00000000) ? 1'b1 : 1'b0 ;
always @(negedge Rst_n or posedge Clk)
begin
if (Rst_n == 1'b0)
begin
PSW <= 7'b0000000 ;
end
else
begin
if (SFR_Wr_i == 1'b1 & Int_AddrA_r == 8'b11010000)
begin
PSW <= Res_Bus[7:1] ;
end
// CY
if ((Status_Wr[7]) == 1'b1)
begin
PSW[7] <= Status_D[7] ;
end
// AC
if ((Status_Wr[6]) == 1'b1)
begin
PSW[6] <= Status_D[6] ;
end
// OV
if ((Status_Wr[5]) == 1'b1)
begin
PSW[2] <= Status_D[5] ;
end
end
end
//--------------------------------------------------------------------------
// B
always @(negedge Rst_n or posedge Clk)
begin
if (Rst_n == 1'b0)
begin
B <= 8'b00000000 ;
B_Wr <= 1'b0 ;
end
else
begin
if (((cInst_is_DIV & ~PCPause) | cInst_is_MUL) & Last_Cycle)
begin
// DIV, MUL
B_Wr <= 1'b1 ;
end
else
begin
B_Wr <= 1'b0 ;
end
if (B_Wr == 1'b1)
begin
B <= B_Q ;
end
if (SFR_Wr_i == 1'b1 & Int_AddrA_r == 8'b11110000)
begin
B <= Res_Bus ;
end
end
end
//--------------------------------------------------------------------------
// ACC
always @(negedge Rst_n or posedge Clk)
begin
if (Rst_n == 1'b0)
begin
ACC <= 8'b00000000 ;
ACC_Wr <= 1'b0 ;
end
else
begin
if ((cInst_is_A_Write & Last_Cycle & ~PCPause) | (cInst_is_DIV & ~PCPause))
begin
ACC_Wr <= 1'b1 ;
end
else
begin
ACC_Wr <= 1'b0 ;
end
if (ACC_Wr == 1'b1)
begin
ACC <= ACC_Q ;
end
if (SFR_Wr_i == 1'b1 & Int_AddrA_r == 8'b11100000)
begin
ACC <= Res_Bus ;
end
if (RAM_Rd_i == 1'b1)
begin
ACC <= RAM_RData ;
end
if (cInst_is_MOVC & Third_Cycle)
begin
// MOVC
ACC <= ROM_Data ;
end
end
end
//--------------------------------------------------------------------------
// MUX
always @(posedge Clk or negedge Rst_n)
begin
if (Rst_n == 1'b0)
begin
AMux_SFR <= 0 ;
BMux_Inst2 <= 0 ;
RMux_PCL <= 0 ;
RMux_PCH <= 0 ;
end
else
begin
AMux_SFR <= 0 ;
BMux_Inst2 <= 0 ;
RMux_PCL <= 0 ;
RMux_PCH <= 0 ;
if ((Int_AddrA[7]) == 1'b1)
begin
AMux_SFR <= 1 ;
end
if (cInst[3:1] == 3'b011)
begin
if (~(cInst[7:4] == 4'b1010 & Second_Cycle))
begin
// Indirect addressing
AMux_SFR <= 0 ;
end
end
if (cInst_is_POP & First_Cycle)
begin
// 11010000 2 POP data addr MOV <dest>,"@SP": DEC SP
AMux_SFR <= 0 ;
end
if (cInst[3:0] == 4'b0011 | cInst[3:0] == 4'b0101)
begin
BMux_Inst2 <= 1 ;
end
if (cInst_is_LCALL | cInst_is_ACALL | ICall)
begin
// LCALL, ACALL, Int
if (First_Cycle)
begin
RMux_PCL <= 1 ;
end
else if (Second_Cycle)
begin
RMux_PCH <= 1 ;
end
end
end
end
//--------------------------------------------------------------------------
// DPTR0, DPTR1, CKCON, Port2_Reg
always @(negedge Rst_n or posedge Clk)
begin
if (Rst_n == 1'b0)
begin
MPAGE <= 8'b00000000 ;
DPTR0 <= {16{1'b0}} ;
DPTR1 <= {16{1'b0}} ;
CKCON <= 8'b00000001 ;
end
else
begin
if (SFR_Wr_i == 1'b1 & Int_AddrA_r == 8'b10010010)
begin
MPAGE <= Res_Bus ;
end
if (SFR_Wr_i == 1'b1 & Int_AddrA_r == 8'b10100000)
begin
MPAGE <= Res_Bus ;
end
if (SFR_Wr_i == 1'b1 & Int_AddrA_r == 8'b10000010)
begin
//DPL0 <= Res_Bus ;
DPTR0[7:0] <= Res_Bus ;
end
if (SFR_Wr_i == 1'b1 & Int_AddrA_r == 8'b10000011)
begin
//DPH0 <= Res_Bus ;
DPTR0[15:8] <= Res_Bus ;
end
if (SFR_Wr_i == 1'b1 & Int_AddrA_r == 8'b10000100)
begin
//DPL1 <= Res_Bus ;
DPTR1[7:0] <= Res_Bus ;
end
if (SFR_Wr_i == 1'b1 & Int_AddrA_r == 8'b10000101)
begin
//DPH1 <= Res_Bus ;
DPTR1[15:8] <= Res_Bus ;
end
if (SFR_Wr_i == 1'b1 & Int_AddrA_r == 8'b10001110)
begin
CKCON <= Res_Bus ;
end
if (Ready)
begin
if (cInst == 8'b10010000 & Second_Cycle)
begin
// 10010000 3 MOV DPTR,#data
if (DPS[0] == 1'b0)
begin
//DPH0 <= cInst1 ;
DPTR0[15:8] <= cInst1 ;
end
else
begin
//DPH1 <= cInst1 ;
DPTR1[15:8] <= cInst1 ;
end
end
if (cInst == 8'b10010000 & Third_Cycle)
begin
if (DPS[0] == 1'b0)
begin
//DPL0 <= cInst2 ;
DPTR0[7:0] <= cInst2 ;
end
else
begin
//DPL1 <= cInst2 ;
DPTR1[7:0] <= cInst2 ;
end
end
if (INC_DPTR)
begin
// 10100011 1 INC DPTR
if (DPS[0] == 1'b0)
begin
DPTR0 <= DPTR0 + 1 ;
end
else
begin
DPTR1 <= DPTR1 + 1 ;
end
end
end
end
end
//--------------------------------------------------------------------------
// INC_DPTR
always @(negedge Rst_n or posedge Clk)
begin
if (Rst_n == 1'b0)
begin
INC_DPTR <= 0 ;
end
else
begin
if (Ready)
begin
INC_DPTR <= cInst_is_INC_DPTR ;
end
end
end
//--------------------------------------------------------------------------
// DPS
always @(negedge Rst_n or posedge Clk)
begin
if (Rst_n == 1'b0)
begin
DPS <= 8'b00000000 ;
end
else
begin
if (SFR_Wr_i == 1'b1 & Int_AddrA_r == 8'b10000110)
begin
DPS <= Res_Bus ;
end
end
end
//--------------------------------------------------------------------------
// Interrupts
assign IStart = Last_Cycle & IPending & ~Inst_Skip & ~PCPause & ~Ri_Stall & ~PSW_Stall & ~RW_Stall ;
// no interrupt in 4 cycle after RETI
always @(negedge Rst_n or posedge Clk)
begin
if (Rst_n == 1'b0)
begin
INT_reject <= 0 ;
end
else
begin
if (cInst_is_RETI)
begin
INT_reject <= 1 ;
end
else
begin
INT_reject <= 0 ;
end
end
end
// IP
always @(negedge Rst_n or posedge Clk)
begin
if (Rst_n == 1'b0)
begin
IP <= 8'b10000000 ;
end
else
begin
if (SFR_Wr_i == 1'b1 & Int_AddrA_r == 8'b10111000)
begin
IP <= Res_Bus ;
end
end
end
// EIP
always @(negedge Rst_n or posedge Clk)
begin
if (Rst_n == 1'b0)
begin
EIP <= 8'b10000000 ;
end
else
begin
if (SFR_Wr_i == 1'b1 & Int_AddrA_r == 8'b11111000)
begin
EIP <= Res_Bus ;
end
end
end
// LPInt, HPInt, IPending, Int_Acc, Int_Trig_r
assign INT_IP = {EIP[3:0], IP[6:0]} ;
always @(negedge Rst_n or posedge Clk)
begin
if (Rst_n == 1'b0)
begin
LPInt <= 0 ;
HPInt <= 0 ;
Int_Trig_r <= {11{1'b0}} ;
IPending <= 0 ;
end
else
begin
if (Ready)
begin
if (ICall)
begin
IPending <= 0 ;
end
else if ((Int_Trig & INT_IP) != 11'b00000000000 & ~HPInt & ~IPending & ~ICall & ~INT_reject)
begin
Int_Trig_r <= Int_Trig & INT_IP ;
IPending <= 1 ;
HPInt <= 1 ;
end
else if (Int_Trig != 11'b00000000000 & ~LPInt & ~HPInt & ~IPending & ~ICall & ~INT_reject)
begin
Int_Trig_r <= Int_Trig ;
IPending <= 1 ;
LPInt <= 1 ;
end
if (cInst_is_RETI)
begin
if (~HPInt)
begin
LPInt <= 0 ;
end
else
begin
HPInt <= 0 ;
end
end
if (ICall & Last_Cycle)
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