it51_core.v
来自「流片过的risc_8051源代码 verilog语言描述的~」· Verilog 代码 · 共 2,022 行 · 第 1/5 页
V
2,022 行
SFR_RData = EIP ; // F8
end
default :
begin
SFR_RData = SFR_RData_Ext ;
end
endcase
end
// SFR_Rd_i
always @(cInst or Second_Cycle or Int_AddrA or Last_Cycle or cInst_is_DR or
cInst_is_Ri or cInst_is_PUSH or iSP or First_Cycle or PCPause or
cInst_is_JB or cInst_is_JBC)
begin
SFR_Rd_i = 1'b0 ;
if (cInst[7:3] == 5'b10101)
begin
// MOV Rn, DA
if (First_Cycle & ~PCPause & (Int_AddrA[7]) == 1'b1)
begin
SFR_Rd_i = 1'b1 ;
end
end
else if (cInst == 8'b10000101 | cInst == 8'b10110101 | cInst_is_JB | cInst_is_JBC)
begin
// MOV DA, DA
// CJNE
// JB
// JBC
if (Second_Cycle & (Int_AddrA[7]) == 1'b1)
begin
SFR_Rd_i = 1'b1 ;
end
end
else
begin
if (Last_Cycle & (Int_AddrA[7]) == 1'b1 & cInst_is_DR & ~cInst_is_Ri & cInst[7:3] != 5'b10001 & (~cInst_is_PUSH | (cInst_is_PUSH & Int_AddrA != iSP)))
begin
SFR_Rd_i = 1'b1 ;
end
end
end
// SFR_Wr_i
always @(Last_Cycle or Int_AddrA or cInst_is_DW or cInst_is_IW or cInst_is_PUSH)
begin
if (Last_Cycle & (Int_AddrA[7]) == 1'b1 & cInst_is_DW & ~cInst_is_IW & ~cInst_is_PUSH)
begin
SFR_Wr_p = 1'b1 ;
end
else
begin
SFR_Wr_p = 1'b0 ;
end
end
always @(posedge Clk or negedge Rst_n)
begin
if (Rst_n == 1'b0)
begin
SFR_Wr_i <= 1'b0 ;
end
else
begin
SFR_Wr_i <= SFR_Wr_p ;
end
end
// SFR_RData_r
always @(posedge Clk or negedge Rst_n)
begin
if (Rst_n == 1'b0)
begin
SFR_RData_r <= {8{1'b0}} ;
end
else
begin
SFR_RData_r <= SFR_RData ;
end
end
//--------------------------------------------------------------------------
// External Memory Access
assign RAM_Cycle = (cInst[7:5] == 3'b111 & cInst[3:2] == 2'b00 & cInst[1:0] != 2'b01 & (PCPaused[0]) == 1'b0) ? 1'b1 : 1'b0 ;
assign RAM_Rd = RAM_Rd_i ;
assign RAM_Wr = RAM_Wr_i ;
assign RAM_WData = ACC ;
always @(negedge Rst_n or posedge Clk)
begin
reg[15:0] tmp;
if (Rst_n == 1'b0)
begin
RAM_Rd_i <= 1'b0 ;
RAM_Wr_i <= 1'b0 ;
end
else
begin
RAM_Wr_i <= 1'b0 ;
if (cInst_is_MOVX_Write & ~PCPause)
begin
RAM_Wr_i <= 1'b1 ;
end
RAM_Rd_i <= 1'b0 ;
if (cInst_is_MOVX_Read & ~PCPause & Ready)
begin
RAM_Rd_i <= 1'b1 ;
end
end
end
always @(cInst or MPAGE or DPTR0 or DPTR1 or DPS or Int_AddrA_r or SFR_Wr_i or
Res_Bus or INC_DPTR or Mem_A or Mem_Wr or PSW or Mem_Din)
begin
if (DPS[0] == 1'b0)
begin
RAM_Addr = DPTR0 ;
end
else
begin
RAM_Addr = DPTR1 ;
end
if ((cInst[1]) == 1'b0)
begin
if (SFR_Wr_i == 1'b1 & Int_AddrA_r == 8'b10000110)
begin
// DPS_SEL Cgange
if ((Res_Bus[0]) == 1'b0)
begin
RAM_Addr = DPTR0 ;
end
else
begin
RAM_Addr = DPTR1 ;
end
end
if (SFR_Wr_i == 1'b1 & Int_AddrA_r == 8'b10000010)
begin
RAM_Addr[7:0] = Res_Bus ;
end
if (SFR_Wr_i == 1'b1 & Int_AddrA_r == 8'b10000011)
begin
RAM_Addr[15:8] = Res_Bus ;
end
if (INC_DPTR)
begin
// 10100011 1 INC DPTR
if (DPS[0] == 1'b0)
begin
RAM_Addr = DPTR0 + 1 ;
end
else
begin
RAM_Addr = DPTR1 + 1 ;
end
end
end
else
begin
RAM_Addr = {MPAGE, Mem_A} ;
if (SFR_Wr_i == 1'b1 & Int_AddrA_r == 8'b10100000)
begin
RAM_Addr[15:8] = Res_Bus ;
end
if (Mem_Wr == 1'b1 & Int_AddrA_r == ({3'b000, PSW[4:3], 2'b00, cInst[0]}))
begin
RAM_Addr[7:0] = Mem_Din ;
end
end
end
//--------------------------------------------------------------------------
// Internal SP (iSP)
always @(SFR_Wr_i or Int_AddrA_r or Res_Bus or SP)
begin
if (SFR_Wr_i == 1'b1 & Int_AddrA_r == 8'b10000001)
begin
//iSP = std_logic_vector(Res_Bus) ;
iSP = Res_Bus ;
end
else
begin
iSP = SP ;
end
end
// SP
always @(negedge Rst_n or posedge Clk)
begin
if (Rst_n == 1'b0)
begin
SP <= 8'b00000111 ;
end
else
begin
if (SFR_Wr_i == 1'b1 & Int_AddrA_r == 8'b10000001)
begin
SP <= Res_Bus ;
end
if (Ready)
begin
if ((cInst_is_RET | cInst_is_RETI) & ~PCPause)
begin
SP <= SP - 2 ;
end
if ((cInst_is_LCALL | cInst_is_ACALL | ICall) & Last_Cycle)
begin
// LCALL, ACALL, ICall
SP <= SP + 2 ;
end
if (cInst_is_PUSH & (PCPaused[0]) == 1'b1)
begin
// 11000000 2 PUSH data addr INC SP: MOV "@SP",<src>
SP <= SP + 1 ;
end
if (cInst_is_POP & Last_Cycle)
begin
// 11010000 2 POP data addr MOV <dest>,"@SP": DEC SP
SP <= SP - 1 ;
end
end
end
end
//--------------------------------------------------------------------------
// Internal Memory Access
// Int_Addr_A
always @(ROM_Data or ICall or cInst or cInst1 or cInst2 or PCPaused or PCPause or
First_Cycle or Third_Cycle or PSW or Mem_A or iSP or
Old_Mem_A or Ready or Int_AddrA_r or cInst_is_LCALL or cInst_is_PUSH or
Second_Cycle or cInst_is_POP or cInst_is_RET or cInst_is_RETI or
cInst_is_ACALL or cInst_is_Ri or cInst_is_Rn or cInst_is_CJNE or
cInst_is_7x or cInst_is_8x or cInst_is_Ax or cInst_is_x3 or cInst_is_x5)
begin
Int_AddrA = 8'bxxxxxxxx ;
Mem_A_Rd = 1'b0 ;
if (cInst[3:0] == 4'b0000 | (cInst[3:0] == 4'b0010 & ((cInst[7]) == 1'b1 | cInst[6:4] == 3'b111)))
begin
if ((cInst1[7]) == 1'b0)
begin
Int_AddrA = {4'b0010, cInst1[6:3]} ;
Mem_A_Rd = 1'b1 ;
end
else
begin
Int_AddrA = {1'b1, cInst1[6:3], 3'b000} ; // BitAddress
Mem_A_Rd = 1'b1 ;
end
end
else
begin
Int_AddrA = cInst1 ;
Mem_A_Rd = 1'b1 ;
end
if (cInst_is_LCALL | ICall)
begin
if (First_Cycle)
begin
//Int_AddrA = std_logic_vector(iSP + 1) ;
Int_AddrA = iSP + 1 ;
Mem_A_Rd = 1'b1 ;
end
else
begin
//Int_AddrA = std_logic_vector(iSP + 2) ;
Int_AddrA = iSP + 2 ;
Mem_A_Rd = 1'b1 ;
end
end
if (cInst_is_PUSH)
begin
// 11000000 2 PUSH data addr INC SP: MOV "@SP",<src>
if (Second_Cycle)
begin
//Int_AddrA = std_logic_vector(iSP) ;
Int_AddrA = iSP ;
Mem_A_Rd = 1'b1 ;
end
else
begin
Int_AddrA = cInst1 ;
Mem_A_Rd = 1'b1 ;
end
end
if (cInst_is_POP)
begin
// 11010000 2 POP data addr MOV <dest>,"@SP": DEC SP
if (Second_Cycle)
begin
Int_AddrA = cInst1 ;
Mem_A_Rd = 1'b1 ;
end
else
begin
//Int_AddrA = std_logic_vector(iSP) ;
Int_AddrA = iSP ;
Mem_A_Rd = 1'b1 ;
end
end
if ((cInst_is_RET | cInst_is_RETI) & ~PCPause)
begin
//Int_AddrA = std_logic_vector(iSP) ;
Int_AddrA = iSP ;
Mem_A_Rd = 1'b1 ;
end
if ((cInst_is_RET | cInst_is_RETI) & PCPause)
begin
//Int_AddrA = std_logic_vector(iSP - 1) ;
Int_AddrA = iSP - 1 ;
Mem_A_Rd = 1'b1 ;
end
if (cInst_is_ACALL)
begin
// ACALL
if (First_Cycle)
begin
//Int_AddrA = std_logic_vector(iSP + 1) ;
Int_AddrA = iSP + 1 ;
Mem_A_Rd = 1'b1 ;
end
else
begin
//Int_AddrA = std_logic_vector(iSP + 2) ;
Int_AddrA = iSP + 2 ;
Mem_A_Rd = 1'b1 ;
end
end
else if (cInst_is_x5)
begin
if (cInst_is_8x & Third_Cycle)
begin
Int_AddrA = cInst2 ;
Mem_A_Rd = 1'b1 ;
end
else
begin
Int_AddrA = cInst1 ;
Mem_A_Rd = 1'b1 ;
end
end
else if (cInst_is_Ri)
begin
// @Ri
if ((PCPaused[0]) == 1'b0)
begin
Int_AddrA = {3'b000, PSW[4:3], 2'b00, cInst[0]} ;
Mem_A_Rd = 1'b1 ;
end
else
begin
Int_AddrA = Mem_A ;
Mem_A_Rd = 1'b1 ;
end
if (cInst_is_CJNE & Second_Cycle)
begin
// CJNE
Int_AddrA = Mem_A ;
Mem_A_Rd = 1'b1 ;
end
if (cInst_is_CJNE & First_Cycle)
begin
// CJNE
Int_AddrA = {3'b000, PSW[4:3], 2'b00, cInst[0]} ;
Mem_A_Rd = 1'b1 ;
end
if (cInst_is_8x & Second_Cycle)
begin
// MOV
Int_AddrA = cInst1 ;
Mem_A_Rd = 1'b1 ;
end
if (cInst_is_Ax & First_Cycle & ~PCPause)
begin
// MOV
Int_AddrA = ROM_Data ;
Mem_A_Rd = 1'b1 ;
end
if (cInst_is_Ax & Second_Cycle)
begin
Int_AddrA = Old_Mem_A ;
Mem_A_Rd = 1'b1 ;
end
if (cInst_is_7x & Second_Cycle)
begin
Int_AddrA = Int_AddrA_r ;
Mem_A_Rd = 1'b1 ;
end
end
else if (cInst_is_x3)
begin
Int_AddrA = cInst1 ;
Mem_A_Rd = 1'b1 ;
end
else if (cInst_is_Rn)
begin
// Rn
Mem_A_Rd = 1'b1 ;
Int_AddrA = {3'b000, PSW[4:3], cInst[2:0]} ;
if (cInst_is_8x & Second_Cycle)
begin
Int_AddrA = cInst1 ;
end
if (cInst_is_Ax & First_Cycle)
begin
Int_AddrA = ROM_Data ;
end
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