it51_core.v
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2,022 行
if (Second_Cycle)
begin
nPC = PC_Plus_cInst1 ;
J_Skip = 1 ;
end
end
if (cInst_is_MOVC)
begin
if (Second_Cycle)
begin
if ((cInst[4]) == 1'b0)
begin
nPC = ACC + oPC ;
end
else
begin
if (DPS[0] == 1'b0)
begin
nPC = DPTR0_Plus_ACC ;
end
else
begin
nPC = DPTR1_Plus_ACC ;
end
end
end
else if (Third_Cycle)
begin
nPC = oPC ;
J_Skip = 1 ;
end
end
if (cInst_is_AJMP | cInst_is_ACALL)
begin
if (Second_Cycle)
begin
nPC[15:11] = PC[15:11] ;
nPC[10:8] = cInst[7:5] ;
nPC[7:0] = cInst1 ;
J_Skip = 1 ;
end
end
if (cInst_is_LJMP | cInst_is_LCALL)
begin
if (Second_Cycle)
begin
nPC[15:8] = cInst1 ;
nPC[7:0] = ROM_Data ;
end
end
if (cInst_is_JC)
begin
if (Next_PSW7 == 1'b1 & Second_Cycle)
begin
nPC = PC_Plus_cInst1 ;
J_Skip = 1 ;
end
end
if (cInst_is_JNC)
begin
if (Next_PSW7 == 1'b0 & Second_Cycle)
begin
nPC = PC_Plus_cInst1 ;
J_Skip = 1 ;
end
end
if (cInst_is_DIV)
begin
if (PCPaused[3:1] == 3'b000 | Div_Rdy == 1'b0)
begin
PCPause = 1 ;
nPC = PC ;
end
end
if (cInst_is_POP | cInst_is_PUSH)
begin
if (First_Cycle & (PCPaused[0]) == 1'b0)
begin
PCPause = 1 ;
nPC = PC ;
end
end
if (cInst_is_RET | cInst_is_RETI)
begin
J_Skip = 1 ;
if (First_Cycle & (PCPaused[0]) == 1'b0)
begin
PCPause = 1 ;
nPC = PC ;
end
end
end
//-
end
//--------------------------------------------------------------------------
// Rst_r_n, RET_r
always @(negedge Rst_n or posedge Clk)
begin
if (Rst_n == 1'b0)
begin
Rst_r_n <= 1'b0 ;
RET_r <= 1'b0 ;
end
else
begin
Rst_r_n <= 1'b1 ;
if (Ready)
begin
if (cInst_is_RET | cInst_is_RETI)
begin
RET_r <= 1'b1 ;
end
else
begin
RET_r <= 1'b0 ;
end
end
end
end
//--------------------------------------------------------------------------
// Current Instruction
always @(negedge Rst_n or posedge Clk)
begin
if (Rst_n == 1'b0)
begin
cInst <= {8{1'b0}} ; // Force NOP at reset.
cInst1 <= {8{1'b0}} ;
cInst2 <= {8{1'b0}} ;
cInst_MCode <= 9'b000000001 ;
// Current Instructure is
NOP <= 1 ;
cInst_is_RET <= 0 ;
cInst_is_RETI <= 0 ;
cInst_is_PUSH <= 0 ;
cInst_is_POP <= 0 ;
cInst_is_ACALL <= 0 ;
cInst_is_LCALL <= 0 ;
cInst_is_Ri <= 0 ;
cInst_is_Rn <= 0 ;
cInst_is_A_Write <= 0 ;
cInst_is_IW <= 0 ;
cInst_is_DW <= 0 ;
cInst_is_DR <= 0 ;
cInst_is_MOVX_Write <= 0 ;
cInst_is_MOVX_Read <= 0 ;
cInst_is_DIV <= 0 ;
cInst_is_MUL <= 0 ;
cInst_is_MOVC <= 0 ;
cInst_is_INC_DPTR <= 0 ;
cInst_is_JC <= 0 ;
cInst_is_JNC <= 0 ;
cInst_is_JZ <= 0 ;
cInst_is_JNZ <= 0 ;
cInst_is_SJMP <= 0 ;
cInst_is_AJMP <= 0 ;
cInst_is_LJMP <= 0 ;
cInst_is_JB <= 0 ;
cInst_is_JNB <= 0 ;
cInst_is_JBC <= 0 ;
cInst_is_CJNE <= 0 ;
cInst_is_DJNE <= 0 ;
cInst_is_DJNZ <= 0 ;
cInst_is_JMP_A_DPTR <= 0 ;
cInst_is_x3 <= 0 ;
cInst_is_x5 <= 0 ;
cInst_is_7x <= 0 ;
cInst_is_8x <= 0 ;
cInst_is_Ax <= 0 ;
end
else
begin
if (~Ready)
begin
end
else if (PCPause & ~cInst_is_PUSH)
begin
end
else if (Rst_r_n == 1'b0 | Inst_Skip | IStart | Ri_Stall | PSW_Stall | RW_Stall)
begin
// Skip/Stall/Flush: NOP insertion
cInst <= {8{1'b0}} ;
cInst_MCode <= 9'b000000001 ;
// Current Instructure is
NOP <= 1 ;
cInst_is_RET <= 0 ;
cInst_is_RETI <= 0 ;
cInst_is_PUSH <= 0 ;
cInst_is_POP <= 0 ;
cInst_is_ACALL <= 0 ;
cInst_is_LCALL <= 0 ;
cInst_is_Ri <= 0 ;
cInst_is_Rn <= 0 ;
cInst_is_A_Write <= 0 ;
cInst_is_IW <= 0 ;
cInst_is_DW <= 0 ;
cInst_is_DR <= 0 ;
cInst_is_MOVX_Write <= 0 ;
cInst_is_MOVX_Read <= 0 ;
cInst_is_DIV <= 0 ;
cInst_is_MUL <= 0 ;
cInst_is_MOVC <= 0 ;
cInst_is_INC_DPTR <= 0 ;
cInst_is_JC <= 0 ;
cInst_is_JNC <= 0 ;
cInst_is_JZ <= 0 ;
cInst_is_JNZ <= 0 ;
cInst_is_SJMP <= 0 ;
cInst_is_AJMP <= 0 ;
cInst_is_LJMP <= 0 ;
cInst_is_JB <= 0 ;
cInst_is_JNB <= 0 ;
cInst_is_JBC <= 0 ;
cInst_is_CJNE <= 0 ;
cInst_is_DJNE <= 0 ;
cInst_is_DJNZ <= 0 ;
cInst_is_JMP_A_DPTR <= 0 ;
cInst_is_x3 <= 0 ;
cInst_is_x5 <= 0 ;
cInst_is_7x <= 0 ;
cInst_is_8x <= 0 ;
cInst_is_Ax <= 0 ;
end
else
begin
if (Last_Cycle)
begin
cInst <= ROM_Data ;
cInst_MCode <= nInst_MCode ;
// Current Instructure is
NOP <= (ROM_Data == 8'b00000000) ;
cInst_is_RET <= (ROM_Data == 8'b00100010) ;
cInst_is_RETI <= (ROM_Data == 8'b00110010) ;
cInst_is_PUSH <= (ROM_Data == 8'b11000000) ;
cInst_is_POP <= (ROM_Data == 8'b11010000) ;
cInst_is_ACALL <= (ROM_Data[4:0] == 5'b10001) ;
cInst_is_LCALL <= (ROM_Data == 8'b00010010) ;
cInst_is_Ri <= ((nInst_MCode[7]) == 1'b1) ;
cInst_is_Rn <= ((nInst_MCode[8]) == 1'b1) ;
cInst_is_A_Write <= ((nInst_MCode[2]) == 1'b1) ;
cInst_is_IW <= ((nInst_MCode[4]) == 1'b1) ;
cInst_is_DW <= ((nInst_MCode[6]) == 1'b1) ;
cInst_is_DR <= ((nInst_MCode[5]) == 1'b1) ;
cInst_is_MOVX_Write <= (ROM_Data[7:2] == 6'b111100 & ROM_Data[1:0] != 2'b01) ;
cInst_is_MOVX_Read <= (ROM_Data[7:2] == 6'b111000 & ROM_Data[1:0] != 2'b01) ;
cInst_is_DIV <= (ROM_Data == 8'b10000100) ;
cInst_is_MUL <= (ROM_Data == 8'b10100100) ;
cInst_is_MOVC <= (ROM_Data[7:5] == 3'b100 & ROM_Data[3:0] == 4'b0011) ;
cInst_is_INC_DPTR <= (ROM_Data == 8'b10100011) ;
cInst_is_JC <= (ROM_Data == 8'b01000000) ;
cInst_is_JNC <= (ROM_Data == 8'b01010000) ;
cInst_is_JZ <= (ROM_Data == 8'b01100000) ;
cInst_is_JNZ <= (ROM_Data == 8'b01110000) ;
cInst_is_SJMP <= (ROM_Data == 8'b10000000) ;
cInst_is_AJMP <= (ROM_Data[4:0] == 5'b00001) ;
cInst_is_LJMP <= (ROM_Data == 8'b00000010) ;
cInst_is_JB <= (ROM_Data == 8'b00100000) ;
cInst_is_JNB <= (ROM_Data == 8'b00110000) ;
cInst_is_JBC <= (ROM_Data == 8'b00010000) ;
cInst_is_CJNE <= (ROM_Data[7:4] == 4'b1011 & ROM_Data[3:2] != 2'b00) ;
cInst_is_DJNZ <= (ROM_Data[7:3] == 5'b11011) ;
cInst_is_DJNE <= (ROM_Data == 8'b11010101) ;
cInst_is_JMP_A_DPTR <= (ROM_Data == 8'b01110011) ;
cInst_is_x3 <= (ROM_Data[3:0] == 4'b0011) ;
cInst_is_x5 <= (ROM_Data[3:0] == 4'b0101) ;
cInst_is_7x <= (ROM_Data[7:4] == 4'b0111) ;
cInst_is_8x <= (ROM_Data[7:4] == 4'b1000) ;
cInst_is_Ax <= (ROM_Data[7:4] == 4'b1010) ;
end
else if (First_Cycle)
begin
cInst1 <= ROM_Data ;
end
else if (Second_Cycle)
begin
cInst2 <= ROM_Data ;
end
end
end
end
//--------------------------------------------------------------------------
// Bit_Pattern
always @(negedge Rst_n or posedge Clk)
begin
if (Rst_n == 1'b0)
begin
Bit_Pattern <= 8'b00000000 ;
end
else
begin
if (First_Cycle)
begin
//case (nInst_Rn_Index)
case (ROM_Data[2:0])
3'b000 :
begin
Bit_Pattern <= 8'b00000001 ;
end
3'b001 :
begin
Bit_Pattern <= 8'b00000010 ;
end
3'b010 :
begin
Bit_Pattern <= 8'b00000100 ;
end
3'b011 :
begin
Bit_Pattern <= 8'b00001000 ;
end
3'b100 :
begin
Bit_Pattern <= 8'b00010000 ;
end
3'b101 :
begin
Bit_Pattern <= 8'b00100000 ;
end
3'b110 :
begin
Bit_Pattern <= 8'b01000000 ;
end
default :
begin
Bit_Pattern <= 8'b10000000 ;
end
endcase
end
end
end
//--------------------------------------------------------------------------
// Stall
assign Inst_Skip = (RET_r == 1'b1) | J_Skip ;
assign Ri_Stall = (~NOP & Last_Cycle & ~PCPause & nInst_is_Ri & cInst_is_DW) ? 1 : 0 ;
assign PSW_Stall = ((~NOP & Last_Cycle & cInst_is_DW & (nInst_is_Ri | nInst_is_Rn) & Int_AddrA == 8'b11010000) | (cInst_is_DIV & ~PCPause)) ? 1 : 0 ;
//not PCPause and
assign RW_Stall = (~NOP & Last_Cycle & ((Mem_Wr_p == 1'b1 & (nInst_is_Ri | nInst_is_RET | nInst_is_RETI | nInst_is_DR)) | (SFR_Wr_p == 1'b1 & nInst_is_DR) | cInst_is_MUL)) ? 1 : 0 ;
//--------------------------------------------------------------------------
// SFR Access
assign SFR_Rd = SFR_Rd_i ;
assign SFR_Wr = SFR_Wr_i ;
assign SFR_Addr = (SFR_Wr_i == 1'b1) ? Int_AddrA_r[6:0] : Int_AddrA[6:0] ;
assign SFR_WData = Res_Bus ;
always @(Int_AddrA or IP or DPTR0 or DPTR1 or DPS or PSW or PSW0 or ACC or
EIP or B or SP or SFR_RData_Ext or CKCON or MPAGE)
begin
case (Int_AddrA)
8'b10111000 :
begin
SFR_RData = IP ;
end
8'b10000010 :
begin
//SFR_RData = DPL0 ; // 82
SFR_RData = DPTR0[7:0] ; // 82
end
8'b10000011 :
begin
//SFR_RData = DPH0 ; // 83
SFR_RData = DPTR0[15:8] ; // 83
end
8'b10000100 :
begin
//SFR_RData = DPL1 ; // 84
SFR_RData = DPTR1[7:0] ; // 84
end
8'b10000101 :
begin
//SFR_RData = DPH1 ; // 85
SFR_RData = DPTR1[15:8] ; // 85
end
8'b10000110 :
begin
SFR_RData = DPS ; // 86
end
8'b10001110 :
begin
SFR_RData = CKCON ; // 8E
end
8'b10010010 :
begin
SFR_RData = MPAGE ; // 92
end
8'b11010000 :
begin
SFR_RData = {PSW, PSW0} ;
end
8'b11100000 :
begin
SFR_RData = ACC ;
end
8'b11110000 :
begin
SFR_RData = B ;
end
8'b10000001 :
begin
//SFR_RData = std_logic_vector(SP) ;
SFR_RData = SP ;
end
8'b11111000 :
begin
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