it51_core.v
来自「流片过的risc_8051源代码 verilog语言描述的~」· Verilog 代码 · 共 2,022 行 · 第 1/5 页
V
2,022 行
else
begin
//PC_Plus_cInst2 <= std_logic_vector(signed(nPC) + signed(cInst2)) ;
PC_Plus_cInst2 <= nPC + cInst2 ;
end
end
end
end
// PCPaused
always @(negedge Rst_n or posedge Clk)
begin
if (Rst_n == 1'b0)
begin
PCPaused <= {4{1'b0}} ;
end
else
begin
if (Ready)
begin
if (PCPause)
begin
PCPaused <= PCPaused + 1 ;
end
else
begin
PCPaused <= {4{1'b0}} ;
end
end
end
end
// oPC
always @(negedge Rst_n or posedge Clk)
begin
if (Rst_n == 1'b0)
begin
oPC <= {16{1'b0}} ;
end
else
begin
if (Ready & cInst_is_MOVC & First_Cycle)
begin
// MOVC
oPC <= PC ;
end
end
end
//--------------------------------------------------------------------------
// Cycle
assign Last_Cycle = (ICall & Third_Cycle) ? 1 : (ICall) ? 0 : (cInst_MCode[1:0] == FCycle & Ready) ? 1 : 0 ;
always @(negedge Rst_n or posedge Clk)
begin
if (Rst_n == 1'b0)
begin
FCycle <= 2'b01 ;
end
else
begin
if (Ready)
begin
if (~PCPause)
begin
if (Last_Cycle)
begin
FCycle <= 2'b01 ;
end
else
begin
FCycle <= FCycle + 1 ;
end
end
end
end
end
// process (Rst_n, Clk)
// begin
// if Rst_n = '0' then
// First_Cycle <= true;
// Second_Cycle <= false;
// Third_Cycle <= false;
// elsif Clk'event and Clk = '1' then
// if Ready then
// if not PCPause then
// if Last_Cycle then
// First_Cycle <= true;
// Second_Cycle <= false;
// Third_Cycle <= false;
// else
// if FCycle = "01" then
// First_Cycle <= false;
// Second_Cycle <= true;
// Third_Cycle <= false;
// end if;
// if FCycle = "10" then
// First_Cycle <= false;
// Second_Cycle <= false;
// Third_Cycle <= true;
// end if;
// end if;
// end if;
// end if;
// end if;
// end process;
assign First_Cycle = (FCycle == 2'b01) ;
assign Second_Cycle = (FCycle == 2'b10) ;
assign Third_Cycle = (FCycle == 2'b11) ;
//--------------------------------------------------------------------------
// NPC (Next PC)
assign DPTR0_Plus_ACC = DPTR0 + ACC ;
assign DPTR1_Plus_ACC = DPTR1 + ACC ;
always @(negedge Rst_n or posedge Clk)
begin
if (Rst_n == 1'b0)
begin
IRQ_Entry <= {16{1'b0}} ;
end
else
begin
IRQ_Entry <= 16'b0000000000000011 ; // INT0
if ((Int_Trig_r[1]) == 1'b1)
begin
IRQ_Entry <= 16'b0000000000001011 ; // TF0
end
else if ((Int_Trig_r[2]) == 1'b1)
begin
IRQ_Entry <= 16'b0000000000010011 ; // INT1
end
else if ((Int_Trig_r[3]) == 1'b1)
begin
IRQ_Entry <= 16'b0000000000011011 ; // TF1
end
else if ((Int_Trig_r[4]) == 1'b1)
begin
IRQ_Entry <= 16'b0000000000100011 ; // TI_0 / RI_0
end
else if ((Int_Trig_r[5]) == 1'b1)
begin
IRQ_Entry <= 16'b0000000000101011 ; // TF2
end
else if ((Int_Trig_r[6]) == 1'b1)
begin
IRQ_Entry <= 16'b0000000000110011 ; // TI_1
end
else if ((Int_Trig_r[7]) == 1'b1)
begin
IRQ_Entry <= 16'b0000000001000011 ; // INT2
end
else if ((Int_Trig_r[8]) == 1'b1)
begin
IRQ_Entry <= 16'b0000000001001011 ; // INT3
end
else if ((Int_Trig_r[9]) == 1'b1)
begin
IRQ_Entry <= 16'b0000000001010011 ; // INT4
end
else if ((Int_Trig_r[10]) == 1'b1)
begin
IRQ_Entry <= 16'b0000000001011011 ; // INT5
end
end
end
always @(PC or Rst_r_n or Ready or RET_r or Mem_A or Old_Mem_A or ICall or
Second_Cycle or Ri_Stall or PSW_Stall or PC_Plus_1 or
cInst or First_Cycle or PCPaused or Div_Rdy or ACC or oPC or DPS[0] or
DPTR0_Plus_ACC or DPTR1_Plus_ACC or Third_Cycle or Next_PSW7 or
PC_Plus_cInst1 or Next_ACC_Z or RW_Stall or Bit_Pattern or
Op_A or PC_Plus_cInst2 or CJNE or DJNZ or cInst1 or ROM_Data or DPS or
cInst_is_Ri or IRQ_Entry or cInst_is_JC or cInst_is_JNC or cInst_is_DIV or
cInst_is_POP or cInst_is_PUSH or cInst_is_RET or cInst_is_RETI or
cInst_is_JB or cInst_is_JBC or cInst_is_JNB or cInst_is_JZ or cInst_is_JNZ or
cInst_is_SJMP or cInst_is_MOVC or cInst_is_AJMP or cInst_is_ACALL or
cInst_is_LJMP or cInst_is_LCALL or cInst_is_JMP_A_DPTR or cInst_is_CJNE or
cInst_is_DJNE or cInst_is_DJNZ)
begin
nPC = PC ;
J_Skip = 0 ;
PCPause = 0 ;
if (Rst_r_n == 1'b0)
begin
nPC = {16{1'b0}} ;
end
else if (~Ready)
begin
nPC = PC ;
end
else if (RET_r == 1'b1)
begin
nPC = ({Mem_A, Old_Mem_A}) ;
end
else if (ICall)
begin
nPC = PC_Plus_1 ;
if (Second_Cycle)
begin
nPC = IRQ_Entry ;
end
end
else
begin
if (~Ri_Stall & ~PSW_Stall & ~RW_Stall)
begin
nPC = PC_Plus_1 ;
end
if (cInst_is_Ri & (PCPaused[0]) == 1'b0 & First_Cycle)
begin
PCPause = 1 ;
nPC = PC ;
end
if (cInst_is_CJNE)
begin
PCPause = 0 ;
nPC = PC ;
// case conv_integer(cInst) is
// when 16#C0# | 16#D0#=> -- PUSH/POP
// if First_Cycle and PCPaused(0) = '0' then
// PCPause <= true;
// NPC <= PC;
// end if;
// when 16#84# => -- DIV
// if PCPaused(3 downto 1) = "000" or Div_Rdy = '0' then
// PCPause <= true;
// NPC <= PC;
// end if;
// when 16#22# | 16#32# => -- RET, RETI
// J_Skip <= true;
// if First_Cycle and PCPaused(0) = '0' then
// PCPause <= true;
// NPC <= PC;
// end if;
// when 16#83# | 16#93# => -- MOVC
// if Second_Cycle then
// if cInst(4) = '0' then
// NPC <= ACC + OPC;
// else
// if DPS_SEL = '0' then
// NPC <= DPTR0_Plus_ACC;
// else
// NPC <= DPTR1_Plus_ACC;
// end if;
// end if;
// elsif Third_Cycle then
// NPC <= OPC;
// J_Skip <= true;
// end if;
// when 16#40# => -- JC
// if Next_PSW7 = '1' and Second_Cycle then
// NPC <= PC_Plus_cInst1;
// J_Skip <= true;
// end if;
// when 16#50# => -- JNC
// if Next_PSW7 = '0' and Second_Cycle then
// NPC <= PC_Plus_cInst1;
// J_Skip <= true;
// end if;
// when 16#60# => -- JZ
// if Next_ACC_Z = '1' and Second_Cycle then
// NPC <= PC_Plus_cInst1;
// J_Skip <= true;
// end if;
// when 16#70# => -- JNZ
// if Next_ACC_Z = '0' and Second_Cycle then
// NPC <= PC_Plus_cInst1;
// J_Skip <= true;
// end if;
// when 16#D8# to 16#DF# => --DJNZ (2 Byte)
// if DJNZ = '1' and Second_Cycle then
// NPC <= PC_Plus_cInst1;
// J_Skip <= true;
// end if;
// when 16#80# => -- SJMP
// if Second_Cycle then
// NPC <= PC_Plus_cInst1;
// J_Skip <= true;
// end if;
// when 16#20# | 16#10# => -- JB, JBC
// if Third_Cycle and (Bit_Pattern and Op_A) /= "00000000" then
// NPC <= PC_Plus_cInst2;
// J_Skip <= true;
// end if;
// when 16#30# =>-- JNB
// if Third_Cycle and (Bit_Pattern and Op_A) = "00000000" then
// NPC <= PC_Plus_cInst2;
// J_Skip <= true;
// end if;
// when 16#B4# to 16#BF# => -- CJNE
// PCPause <= false;
// NPC <= PC;
// if not Ri_Stall and not PSW_Stall and not RW_Stall then
// NPC <= PC_Plus_1;
// end if;
// if Third_Cycle and CJNE = '1' then -- CJNE
// NPC <= PC_Plus_cInst2;
// J_Skip <= true;
// end if;
// when 16#D5# => -- DJNE (3 byte)
// if Third_Cycle and DJNZ = '1' then -- DJNZ
// NPC <= PC_Plus_cInst2;
// J_Skip <= true;
// end if;
// when 16#01# | 16#21# | 16#41# |16#61# |
// 16#81# | 16#A1# | 16#C1# |16#E1# | -- AJMP
// 16#11# | 16#31# | 16#51# |16#71# |
// 16#91# | 16#B1# | 16#D1# |16#F1# => -- ACALL
// if Second_Cycle then
// NPC(15 downto 11) <= PC(15 downto 11);
// NPC(10 downto 8) <= cInst(7 downto 5);
// NPC( 7 downto 0) <= cInst1;
// J_Skip <= true;
// end if;
// when 16#02# | 16#12# => -- LJMP, LCALL
// if Second_Cycle then
// NPC(15 downto 8) <= cInst1;
// NPC( 7 downto 0) <= nInst;
// end if;
// when 16#73# => -- JMP @A+DPTR
// if DPS_SEL = '0' then
// NPC <= DPTR0_Plus_ACC;
// else
// NPC <= DPTR1_Plus_ACC;
// end if;
// J_Skip <= true;
// when others =>
// null;
// end case;
//-
if (~Ri_Stall & ~PSW_Stall & ~RW_Stall)
begin
nPC = PC_Plus_1 ;
end
if (Third_Cycle & CJNE == 1'b1)
begin
// CJNE
nPC = PC_Plus_cInst2 ;
J_Skip = 1 ;
end
end
if (cInst_is_JMP_A_DPTR)
begin
if (DPS[0] == 1'b0)
begin
nPC = DPTR0_Plus_ACC ;
end
// elsif Ri_Stall or PSW_Stall or RW_Stall then
// NPC <= PC_Plus_1;
else
begin
nPC = DPTR1_Plus_ACC ;
end
J_Skip = 1 ;
end
if (cInst_is_DJNE)
begin
if (DJNZ == 1'b1 & Third_Cycle)
begin
// DJNZ
nPC = PC_Plus_cInst2 ;
J_Skip = 1 ;
end
end
if (cInst_is_DJNZ)
begin
if (DJNZ == 1'b1 & Second_Cycle)
begin
nPC = PC_Plus_cInst1 ;
J_Skip = 1 ;
end
end
if (cInst_is_JB | cInst_is_JBC)
begin
if (Third_Cycle & (Bit_Pattern & Op_A) != 8'b00000000)
begin
nPC = PC_Plus_cInst2 ;
J_Skip = 1 ;
end
end
if (cInst_is_JNB)
begin
if (Third_Cycle & (Bit_Pattern & Op_A) == 8'b00000000)
begin
nPC = PC_Plus_cInst2 ;
J_Skip = 1 ;
end
end
if (cInst_is_JZ)
begin
if (Next_ACC_Z == 1'b1 & Second_Cycle)
begin
nPC = PC_Plus_cInst1 ;
J_Skip = 1 ;
end
end
if (cInst_is_JNZ)
begin
if (Next_ACC_Z == 1'b0 & Second_Cycle)
begin
nPC = PC_Plus_cInst1 ;
J_Skip = 1 ;
end
end
if (cInst_is_SJMP)
begin
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