it51_uart.v

流片过的risc_8051源代码 verilog语言描述的~

         begin
            SCON[0] <= Data_In[0] ; 
            SCON[2] <= Data_In[2] ; 
         end 
         if (SCON[7:6] == 2'b00 & Tick6 == 1'b1)
         begin
            if ((SCON[4]) == 1'b1 & (SCON[0]) == 1'b0 & RX_Bit_Cnt == 0)
            begin
               RX_Shifting <= 1'b1 ; 
               RX_Bit_Cnt <= 1 ; 
            end
            else if (RX_Bit_Cnt != 0)
            begin
               if (RX_Bit_Cnt == 8)
               begin
                  RX_Shifting <= 1'b0 ; 
                  SCON[0] <= 1'b1 ; 
                  SBUF[6:0] <= RX_ShiftReg[7:1] ; 
                  SBUF[7] <= RX_Filtered ; 
                  RX_Bit_Cnt <= 0 ; 
               end
               else
               begin
                  RX_ShiftReg[7:0] <= RX_ShiftReg[8:1] ; 
                  RX_ShiftReg[7] <= RX_Filtered ; 
                  RX_Bit_Cnt <= RX_Bit_Cnt + 1 ; 
               end 
            end 
         end
         else if (Baud16R_i == 1'b1 & (SCON[4]) == 1'b1)
         begin
            if (RX_Bit_Cnt == 0 & (RX_Filtered == 1'b1 | Bit_Phase == 4'b0111))
            begin
               Bit_Phase <= 4'b0000 ; 
            end
            else
            begin
               Bit_Phase <= Bit_Phase + 1 ; 
            end 
            if (RX_Bit_Cnt == 0)
            begin
               if (Bit_Phase == 4'b0111)
               begin
                  RX_Bit_Cnt <= RX_Bit_Cnt + 1 ; 
               end 
            end
            else if (Bit_Phase == 4'b1111)
            begin
               RX_Bit_Cnt <= RX_Bit_Cnt + 1 ; 
               if (((SCON[7]) == 1'b0 & RX_Bit_Cnt == 9) | ((SCON[7]) == 1'b1 & RX_Bit_Cnt == 10))
               begin
                  // Stop bit
                  RX_Bit_Cnt <= 0 ; 
                  if (~((SCON[5]) == 1'b1 & (RX_ShiftReg[8]) == 1'b0))
                  begin
                     SCON[0] <= 1'b1 ; 
                  end 
                  if (SCON[7:5] == 3'b010)
                  begin
                     SCON[2] <= RX_Filtered ; 
                  end 
                  if ((SCON[7]) == 1'b1)
                  begin
                     SCON[2] <= RX_ShiftReg[8] ; 
                  end 
                  SBUF <= RX_ShiftReg[7:0] ; 
               end
               else
               begin
                  RX_ShiftReg[7:0] <= RX_ShiftReg[8:1] ; 
                  if ((SCON[7]) == 1'b1)
                  begin
                     RX_ShiftReg[8] <= RX_Filtered ; 
                  end
                  else
                  begin
                     RX_ShiftReg[7] <= RX_Filtered ; 
                  end 
               end 
            end 
         end 
      end 
   end 

   // Transmit bit tick
   always @(posedge Clk or negedge Rst_n)
   begin
      reg[3:0] TX_Cnt; 
      if (Rst_n == 1'b0)
      begin
         TX_Cnt <= 4'b0000; 
         TX_Tick <= 1'b0 ; 
      end
      else
      begin
         TX_Tick <= 1'b0 ; 
         if (Baud16T_i == 1'b1)
         begin
            if (TX_Cnt == 4'b1111)
            begin
               TX_Tick <= 1'b1 ; 
            end 
            TX_Cnt <= TX_Cnt + 1; 
         end 
      end 
   end 
   // Transmit state machine
   assign RXD_IsO = TX_Shifting ;
   assign TI = SCON[1] ;
   assign TXD = TXD_i ;

   always @(posedge Clk or negedge Rst_n)
   begin
      if (Rst_n == 1'b0)
      begin
         SCON[1] <= 1'b0 ; 
         TX_Bit_Cnt <= 0 ; 
         TX_ShiftReg <= {9{1'b0}} ; 
         TX_Data <= {8{1'b0}} ; 
         TX_Start <= 1'b0 ; 
         TX_Shifting <= 1'b0 ; 
         TXD_i <= 1'b1 ; 
         RXD_O <= 1'b1 ; 
      end
      else
      begin
         if (SC_Wr == 1'b1)
         begin
            SCON[1] <= Data_In[1] ; 
         end 
         if (SB_Wr == 1'b1)
         begin
            TX_Data <= Data_In ; 
            TX_Start <= 1'b1 ; 
         end 
         if (Tick6 == 1'b1 & (RX_Shifting == 1'b1 | TX_Shifting == 1'b1))
         begin
            TXD_i <= ~TXD_i ; 
         end 
         if (SCON[7:6] == 2'b00 & Tick6 == 1'b1 & (TXD_i == 1'b0 | TX_Bit_Cnt == 0))
         begin
            if (TX_Start == 1'b1 & TX_Bit_Cnt == 0)
            begin
               TX_ShiftReg[6:0] <= TX_Data[7:1] ; 
               TX_Shifting <= 1'b1 ; 
               TX_Bit_Cnt <= 1 ; 
               TX_Start <= 1'b0 ; 
               RXD_O <= TX_Data[0] ; 
            end
            else if (TX_Bit_Cnt != 0)
            begin
               if (TX_Bit_Cnt == 8)
               begin
                  TX_Shifting <= 1'b0 ; 
                  SCON[1] <= 1'b1 ; 
                  RXD_O <= 1'b1 ; 
                  TX_Bit_Cnt <= 0 ; 
               end
               else
               begin
                  RXD_O <= TX_ShiftReg[0] ; 
                  SCON[1] <= 1'b1 ; 
                  TX_Bit_Cnt <= TX_Bit_Cnt + 1 ; 
               end 
               TX_ShiftReg[7:0] <= TX_ShiftReg[8:1] ; 
            end 
         end
         else if (TX_Tick == 1'b1)
         begin
            case (TX_Bit_Cnt)
               0 :
                        begin
                           if (TX_Start == 1'b1)
                           begin
                              TX_Bit_Cnt <= 1 ; 
                           end 
                           TXD_i <= 1'b1 ; 
                        end
               1 :
                        begin
                           // Start bit
                           TX_ShiftReg[7:0] <= TX_Data ; 
                           TX_ShiftReg[8] <= SCON[3] ; 
                           TX_Start <= 1'b0 ; 
                           TXD_i <= 1'b0 ; 
                           TX_Bit_Cnt <= TX_Bit_Cnt + 1 ; 
                        end
               default :
                        begin
                           TX_Bit_Cnt <= TX_Bit_Cnt + 1 ; 
                           if ((SCON[7]) == 1'b1)
                           begin
                              if (TX_Bit_Cnt == 10)
                              begin
                                 TX_Bit_Cnt <= 0 ; 
                                 SCON[1] <= 1'b1 ; 
                              end 
                           end
                           else
                           begin
                              if (TX_Bit_Cnt == 9)
                              begin
                                 TX_Bit_Cnt <= 0 ; 
                                 SCON[1] <= 1'b1 ; 
                              end 
                           end 
                           TXD_i <= TX_ShiftReg[0] ; 
                           TX_ShiftReg[7:0] <= TX_ShiftReg[8:1] ; 
                        end
            endcase 
         end 
      end 
   end 

   // Tick generator
   always @(posedge Clk or negedge Rst_n)
   begin
      reg[2:0] Prescaler; 
      if (Rst_n == 1'b0)
      begin
         Prescaler <= {3{1'b0}}; 
         Tick6 <= 1'b0 ; 
      end
      else
      begin
         Tick6 <= 1'b0 ; 
         if (Prescaler == 3'b101)
         begin
            Prescaler <= 3'b000; 
            Tick6 <= 1'b1 ; 
         end
         else
         begin
            Prescaler <= Prescaler + 1; 
         end 
      end
      //			if FastCount then
      //				Tick6 <= '1';
      //			end if; 
   end 
endmodule