it51_addsub.v

流片过的risc_8051源代码 verilog语言描述的~

module AddSub1(
	A,
	B,
	Sub,
	Carry_In,
	Res,
	Carry
);
      input A; 
      input B; 
      input Sub; 
      input Carry_In; 
      output Res; 
      output Carry; 

      reg Res;
      reg Carry;

      always @(Sub or A or B or Carry_In)
	if(Sub)
	  {Carry,Res} = A - B + Carry_In;
	else
	  {Carry,Res} = A + B + Carry_In;
endmodule

module AddSub3(
	A,
	B,
	Sub,
	Carry_In,
	Res,
	Carry
);
      input [2:0] A; 
      input [2:0] B; 
      input Sub; 
      input Carry_In; 
      output [2:0] Res; 
      output Carry; 

      reg [2:0] Res;
      reg Carry;

      always @(Sub or A or B or Carry_In)
	if(Sub)
	  {Carry,Res} = A - B + Carry_In;
	else
	  {Carry,Res} = A + B + Carry_In;

endmodule

module AddSub4(
	A,
	B,
	Sub,
	Carry_In,
	Res,
	Carry
);
      input [3:0] A; 
      input [3:0] B; 
      input Sub; 
      input Carry_In; 
      output [3:0] Res; 
      output Carry; 

      reg [3:0] Res;
      reg Carry;

      always @(Sub or A or B or Carry_In)
	if(Sub)
	  {Carry,Res} = A - B + Carry_In;
	else
	  {Carry,Res} = A + B + Carry_In;

endmodule

module AddSub8(
	A,
	B,
	Sub,
	Carry_In,
	Res,
	Carry
);
      input [7:0] A; 
      input [7:0] B; 
      input Sub; 
      input Carry_In; 
      output [7:0] Res; 
      output Carry; 

      reg [7:0] Res;
      reg Carry;

      always @(Sub or A or B or Carry_In)
	if(Sub)
	  {Carry,Res} = A - B + Carry_In;
	else
	  {Carry,Res} = A + B + Carry_In;

endmodule