it51_glue.v

流片过的risc_8051源代码 verilog语言描述的~

//-----------------------------------------------------------------------------
//   IT51 (Improved-T51)                                                     --
//                                                                           --
//   VERSION: 030723                                                         --
//                                                                           --
//   Contact: [e-mail]                                             --
//                                                                           --
//-----------------------------------------------------------------------------
//                                                                           --
//  IT51 - Improved T51 (VHDL 1-Cycle 8051 Compatible Microcontroller)       --
//  Copyright (c) 2001-2002 Daniel Wallner ([e-mail])             --
//                          Yung-Fu Chen ([e-mail])           --
//                                                                           --
//-----------------------------------------------------------------------------
//  FETURE                                                                   --
//     . IT51_top interface is similar to synopsys DW8051                    --
//     . High-Performance 1-Cycle 8051                                       --
//     . instruction compatible with standard DW8051                         --
//     . 256 byte internal data memory                                       --
//     . up to 64KB external data memory                                     --
//     . up to 64KB internal program memory                                  --
//     . export sfr-bus                                                      --
//     . no dual-port memory used                                            --
//     . no watch-dog timer                                                  --
//     . dual DPTR (DPTR0, DPTR1), refer to DW8051                           --
//     . sleep mode support, refer to DW8051                                 --
//     . no stop mode                                                        --
//     . six external interrupt, refer to DW8051                             --
//     . pass all DW8051 test-pattern                                        --
//     . UART/Timer are not fully tested yet                                 --
//     . no internal tri-state bus                                           --
//     . 2-Cycle MUL Instruction                                             --
//                                                                           --
//-----------------------------------------------------------------------------
//                                                                           --
//  IT51_top (Interface Compatible with Synopsys DW8051)                     --
//     |                                                                     --
//     +-- IT51_core (Control Unit)                                          --
//     |       |                                                             --
//     |       +-- IT51_ALU (ALU)                                            --
//     |               |                                                     --
//     |               +-- IT51_MD (MUL/DIV)                                 --
//     |                                                                     --
//     +-- IT51_Glue (Glue Logic)                                            --
//     |                                                                     --
//     +-- IT51_TC01 (Timer/Counter-1)                                       --
//     |                                                                     --
//     +-- IT51_TC2 (Timer/Counter-2)                                        --
//     |                                                                     --
//     +-- IT51_UART (UART)                                                  --
//                                                                           --
//-----------------------------------------------------------------------------
// ============================================================================
// The original T51 license is listed below:
// ============================================================================
//
// 8051 compatible microcontroller core
//
// Version : 0218
//
// Copyright (c) 2001-2002 Daniel Wallner ([e-mail])
//
// All rights reserved
//
// Redistribution and use in source and synthezised forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
// Redistributions in synthesized form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
//
// Neither the name of the author nor the names of other contributors may
// be used to endorse or promote products derived from this software without
// specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
// THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
// PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
// Please report bugs to the author, but before you do so, please
// make sure that this is not a derivative work and that
// you have the latest version of this file.
//
// The latest version of this file can be found at:
//	http://www.opencores.org/cvsweb.shtml/t51/
//
// Limitations :
//
// File history :
//
// ============================================================================
//

module IT51_Glue (Clk, Rst_n, INT0, INT1, INT2, INT3, INT4, INT5, RI, TI, OF0, OF1, OF2, IO_Wr, IO_Rd, IO_CS, IO_Addr, IO_Addr_r, IO_WData, IO_RData, Int_Acc, Int_Trig, R0, R1, SMOD, TMOD_Sel, TL0_Sel, TL1_Sel, TH0_Sel, TH1_Sel, T2CON_Sel, RCAP2L_Sel, RCAP2H_Sel, TL2_Sel, TH2_Sel, SCON_Sel, SBUF_Sel, TMOD_Wr, TL0_Wr, TL1_Wr, TH0_Wr, TH1_Wr, T2CON_Wr, RCAP2L_Wr, RCAP2H_Wr, TL2_Wr, TH2_Wr, SCON_Wr, SBUF_Wr, Idle_n, Stop_n);

   // included from package it51_pack
   input Clk; 
   input Rst_n; 
   input INT0; // edge  or level, active low
   input INT1; // edge  or level, active low
   input INT2; // edge, active high
   input INT3; // edge, active low
   input INT4; // edge, active high
   input INT5; // edge, active low
   input RI; 
   input TI; 
   input OF0; 
   input OF1; 
   input OF2; 
   input IO_Wr; 
   input IO_Rd; 
   output IO_CS; 
   reg IO_CS;
   input[6:0] IO_Addr; 
   input[6:0] IO_Addr_r; 
   input[7:0] IO_WData; 
   output[7:0] IO_RData; 
   reg[7:0] IO_RData;
   input[10:0] Int_Acc; 
   output[10:0] Int_Trig; 
   wire[10:0] Int_Trig;
   output R0; 
   wire R0;
   output R1; 
   wire R1;
   output SMOD; 
   wire SMOD;
   output TMOD_Sel; 
   wire TMOD_Sel;
   output TL0_Sel; 
   wire TL0_Sel;
   output TL1_Sel; 
   wire TL1_Sel;
   output TH0_Sel; 
   wire TH0_Sel;
   output TH1_Sel; 
   wire TH1_Sel;
   output T2CON_Sel; 
   wire T2CON_Sel;
   output RCAP2L_Sel; 
   wire RCAP2L_Sel;
   output RCAP2H_Sel; 
   wire RCAP2H_Sel;
   output TL2_Sel; 
   wire TL2_Sel;
   output TH2_Sel; 
   wire TH2_Sel;
   output SCON_Sel; 
   wire SCON_Sel;
   output SBUF_Sel; 
   wire SBUF_Sel;
   output TMOD_Wr; 
   wire TMOD_Wr;
   output TL0_Wr; 
   wire TL0_Wr;
   output TL1_Wr; 
   wire TL1_Wr;
   output TH0_Wr; 
   wire TH0_Wr;
   output TH1_Wr; 
   wire TH1_Wr;
   output T2CON_Wr; 
   wire T2CON_Wr;
   output RCAP2L_Wr; 
   wire RCAP2L_Wr;
   output RCAP2H_Wr; 
   wire RCAP2H_Wr;
   output TL2_Wr; 
   wire TL2_Wr;
   output TH2_Wr; 
   wire TH2_Wr;
   output SCON_Wr; 
   wire SCON_Wr;
   output SBUF_Wr; 
   wire SBUF_Wr;
   output Idle_n; 
   wire Idle_n;
   output Stop_n; 
   wire Stop_n;

   reg[7:0] IE; 
   reg[7:0] TCON; 
   reg[7:0] PCON; 
   reg[1:0] Int0_r; 
   reg[1:0] Int1_r; 
   reg[1:0] Int2_r; 
   reg[1:0] Int3_r; 
   reg[1:0] Int4_r; 
   reg[1:0] Int5_r; 
   wire[10:0] Int_Trig_i; 
   reg[7:0] EXIF; 
   reg[7:0] EIE; 
   wire TMOD_Sel_i; 
   reg TMOD_Sel_r; 
   wire TL0_Sel_i; 
   reg TL0_Sel_r; 
   wire TL1_Sel_i; 
   reg TL1_Sel_r; 
   wire TL2_Sel_i; 
   reg TL2_Sel_r; 
   wire TH0_Sel_i; 
   reg TH0_Sel_r; 
   wire TH1_Sel_i; 
   reg TH1_Sel_r; 
   wire TH2_Sel_i; 
   reg TH2_Sel_r; 
   wire T2CON_Sel_i; 
   reg T2CON_Sel_r; 
   wire RCAP2L_Sel_i; 
   reg RCAP2L_Sel_r; 
   wire RCAP2H_Sel_i; 
   reg RCAP2H_Sel_r; 
   wire SCON_Sel_i; 
   reg SCON_Sel_r; 
   wire SBUF_Sel_i; 
   reg SBUF_Sel_r; 

   assign R0 = TCON[4] ;
   assign R1 = TCON[6] ;
   assign SMOD = PCON[7] ;
   assign Stop_n = ~PCON[1] ;
   assign Idle_n = ~PCON[0] ;
   assign Int_Trig = Int_Trig_i ;

   // Stop/IDLE
   always @(negedge Rst_n or posedge Clk)
   begin
      if (Rst_n == 1'b0)
      begin
         PCON <= 8'b00110000 ; 
      end
      else
      begin
         if (IO_Wr == 1'b1 & IO_Addr_r == 7'b0000111)
         begin
            PCON <= IO_WData ; 
         end 
         if (PCON[1] == 1'b0)
         begin
            if (PCON[0] == 1'b1)
            begin
               if (Int_Trig_i != 11'b00000000000)
               begin
                  PCON[0] <= 1'b0 ; 
               end 
            end 
         end 
      end 
   end 

   // Registers/Interrupts
   always @(IO_Addr or TCON or PCON or IE or EXIF or EIE)
   begin
      case (IO_Addr)
         7'b0001000 :
                  begin
                     IO_RData = TCON ; 
                  end
         7'b0000111 :
                  begin
                     IO_RData = PCON ; 
                  end
         7'b0101000 :
                  begin
                     IO_RData = IE ; 
                  end
         7'b0010001 :
                  begin
                     IO_RData = EXIF ; 
                  end
         7'b1101000 :
                  begin
                     IO_RData = EIE ; 
                  end
         default :
                  begin
                     IO_RData = 8'bxxxxxxxx ; 
                  end
      endcase 
      case (IO_Addr)
         7'b0001000 :
                  begin
                     IO_CS = 1'b1 ; 
                  end
         7'b0000111 :
                  begin
                     IO_CS = 1'b1 ; 
                  end
         7'b0101000 :
                  begin
                     IO_CS = 1'b1 ; 
                  end
         7'b0010001 :
                  begin
                     IO_CS = 1'b1 ; 
                  end
         7'b1101000 :
                  begin
                     IO_CS = 1'b1 ; 
                  end
         default :
                  begin
                     IO_CS = 1'b0 ; 
                  end
      endcase 
   end 

   always @(negedge Rst_n or posedge Clk)
   begin
      if (Rst_n == 1'b0)
      begin
         EIE <= 8'b11100000 ; 
         EXIF <= 8'b00001000 ; 
         IE <= 8'b00000000 ; 
         TCON <= 8'b00000000 ; 
         Int0_r <= 2'b11 ; 
         Int1_r <= 2'b11 ; 
         Int2_r <= 2'b00 ;