it51_top.v

流片过的risc_8051源代码 verilog语言描述的~

   wire OF2; 
   // YFC
   wire RAM_Cycle; 
   wire rst_n; 
   reg por_n_del1; 
   reg por_n_del2; 
   wire sfr_CS_Glue; 
   wire sfr_rd_i; 
   wire sfr_wr_i; 
   wire[6:0] sfr_addr_i; 
   reg[6:0] sfr_addr_r; 
   wire[7:0] sfr_data_out_i; 
   wire[7:0] sfr_data_in_i; 
   wire[7:0] sfr_data_in_Glue; 
   wire[7:0] sfr_data_in_TC01; 
   wire[7:0] sfr_data_in_TC2; 
   wire[7:0] sfr_data_in_UART; 
   wire INT0; 
   wire INT1; 
   wire INT3; 
   wire INT5; 
   reg[7:0] ROM_Data_r; 
   reg[15:0] RAM_Addr_r; 
   wire[7:0] core_iRAM_Addr; 
   wire core_iRAM_Rd; 
   wire core_iRAM_Wr; 
   wire[7:0] core_iRAM_RData; 
   wire[7:0] core_iRAM_WData; 

   wire rxd_iso;

   assign INT0 = int0_n ;
   assign INT1 = int1_n ;
   assign INT3 = int3_n ;
   assign INT5 = int5_n ;
   assign mem_rd_n = ~RAM_Rd ;
   assign mem_wr_n = ~RAM_Wr ;
   assign mem_addr = RAM_Addr_r ;
   assign stop_mode_n = Stop_n ;
   assign idle_mode_n = Idle_n ;
   assign sfr_data_in_i = (sfr_CS_Glue == 1'b1) ? sfr_data_in_Glue : ((TMOD_Sel | TL0_Sel | TL1_Sel | TH0_Sel | TH1_Sel) == 1'b1) ? sfr_data_in_TC01 : ((T2CON_Sel | RCAP2L_Sel | RCAP2H_Sel | TL2_Sel | TH2_Sel) == 1'b1) ? sfr_data_in_TC2 : ((SCON_Sel | SBUF_Sel) == 1'b1) ? sfr_data_in_UART : sfr_data_in ;
   assign sfr_data_out = sfr_data_out_i ;
   assign sfr_addr[7] = 1'b1 ;
   assign sfr_addr[6:0] = sfr_addr_i ;
   assign sfr_wr = sfr_wr_i ;
   assign sfr_rd = sfr_rd_i ;
   assign irom_rd_n = 1'b0 ;
   assign irom_cs_n = 1'b0 ;
   assign iram_addr = core_iRAM_Addr ;
   assign iram_data_in = core_iRAM_WData ;
   assign iram_rd_n = ~core_iRAM_Rd ;
   assign iram_we1_n = 1'b1 ;
   assign iram_we2_n = ~core_iRAM_Wr ;
   assign core_iRAM_RData = iram_data_out ;
   //---------------------------------------------------------
   // YFC
   //---------------------------------------------------------
   assign rst_n = por_n & por_n_del2 ;
   assign rst_out_n = por_n & por_n_del2 ;

   always @(posedge clk or negedge rst_n)
   begin : por_del_proc
      if (rst_n == 1'b0)
      begin
         por_n_del1 <= 1'b1 ; 
         por_n_del2 <= 1'b1 ; 
         ROM_Data_r <= {8{1'b0}} ; 
         RAM_Addr_r <= {16{1'b0}} ; 
      end
      else
      begin
         por_n_del1 <= por_n ; 
         por_n_del2 <= por_n_del1 ; 
         ROM_Data_r <= irom_data_out ; 
         RAM_Addr_r <= RAM_Addr ; 
      end 
   end 

   //---------------------------------------------------------
   always @(posedge clk or negedge rst_n)
   begin
      if (rst_n == 1'b0)
      begin
         sfr_addr_r <= {7{1'b0}} ; 
      end
      else
      begin
         sfr_addr_r <= sfr_addr_i ; 
      end 
   end 
   IT51_core core51 (
      .Clk(clk), 
      .Rst_n(rst_n), 
      .Idle_n(Idle_n), 
      .ROM_Addr(irom_addr), 
      .ROM_Data(ROM_Data_r), 
      .RAM_Addr(RAM_Addr), 
      .RAM_RData(mem_data_in), 
      .RAM_WData(mem_data_out), 
      .RAM_Cycle(RAM_Cycle), 
      .RAM_Rd(RAM_Rd), 
      .RAM_Wr(RAM_Wr), 
      .iRAM_Addr(core_iRAM_Addr), 
      .iRAM_Rd(core_iRAM_Rd), 
      .iRAM_Wr(core_iRAM_Wr), 
      .iRAM_RData(core_iRAM_RData), 
      .iRAM_WData(core_iRAM_WData), 
      .Int_Trig(Int_Trig), 
      .Int_Acc(Int_Acc), 
      .SFR_Rd(sfr_rd_i), 
      .SFR_Wr(sfr_wr_i), 
      .SFR_Addr(sfr_addr_i), 
      .SFR_WData(sfr_data_out_i), 
      .SFR_RData_Ext(sfr_data_in_i)
   ); 
   IT51_Glue glue51 (
      .Clk(clk), 
      .Rst_n(rst_n), 
      .IO_Wr(sfr_wr_i), 
      .IO_Rd(sfr_rd_i), 
      .IO_CS(sfr_CS_Glue), 
      .IO_Addr(sfr_addr_i), 
      .IO_Addr_r(sfr_addr_r), 
      .IO_WData(sfr_data_out_i), 
      .IO_RData(sfr_data_in_Glue), 
      .INT0(INT0), 
      .INT1(INT1), 
      .INT2(int2), 
      .INT3(INT3), 
      .INT4(int4), 
      .INT5(INT5), 
      .RI(RI), 
      .TI(TI), 
      .OF0(OF0), 
      .OF1(OF1), 
      .OF2(OF2), 
      .Int_Acc(Int_Acc), 
      .R0(R0), 
      .R1(R1), 
      .SMOD(SMOD), 
      .TMOD_Sel(TMOD_Sel), 
      .TL0_Sel(TL0_Sel), 
      .TL1_Sel(TL1_Sel), 
      .TH0_Sel(TH0_Sel), 
      .TH1_Sel(TH1_Sel), 
      .T2CON_Sel(T2CON_Sel), 
      .RCAP2L_Sel(RCAP2L_Sel), 
      .RCAP2H_Sel(RCAP2H_Sel), 
      .TL2_Sel(TL2_Sel), 
      .TH2_Sel(TH2_Sel), 
      .SCON_Sel(SCON_Sel), 
      .SBUF_Sel(SBUF_Sel), 
      .TMOD_Wr(TMOD_Wr), 
      .TL0_Wr(TL0_Wr), 
      .TL1_Wr(TL1_Wr), 
      .TH0_Wr(TH0_Wr), 
      .TH1_Wr(TH1_Wr), 
      .T2CON_Wr(T2CON_Wr), 
      .RCAP2L_Wr(RCAP2L_Wr), 
      .RCAP2H_Wr(RCAP2H_Wr), 
      .TL2_Wr(TL2_Wr), 
      .TH2_Wr(TH2_Wr), 
      .SCON_Wr(SCON_Wr), 
      .SBUF_Wr(SBUF_Wr), 
      .Int_Trig(Int_Trig), 
      .Idle_n(Idle_n), 
      .Stop_n(Stop_n)
   ); 
   IT51_TC01 tc01 (
      .Clk(clk), 
      .Rst_n(rst_n), 
      .T0(t0), 
      .T1(t1), 
      .INT0(int0_n), 
      .INT1(int1_n), 
      .M_Sel(TMOD_Sel), 
      .H0_Sel(TH0_Sel), 
      .L0_Sel(TL0_Sel), 
      .H1_Sel(TH1_Sel), 
      .L1_Sel(TL1_Sel), 
      .R0(R0), 
      .R1(R1), 
      .M_Wr(TMOD_Wr), 
      .H0_Wr(TH0_Wr), 
      .L0_Wr(TL0_Wr), 
      .H1_Wr(TH1_Wr), 
      .L1_Wr(TL1_Wr), 
      .Data_In(sfr_data_out_i), 
      .Data_Out(sfr_data_in_TC01), 
      .OF0(OF0), 
      .OF1(OF1)
   ); 
   IT51_TC2 tc2 (
      .Clk(clk), 
      .Rst_n(rst_n), 
      .T2(t2), 
      .T2EX(t2ex), 
      .C_Sel(T2CON_Sel), 
      .CH_Sel(RCAP2H_Sel), 
      .CL_Sel(RCAP2L_Sel), 
      .H_Sel(TH2_Sel), 
      .L_Sel(TL2_Sel), 
      .C_Wr(T2CON_Wr), 
      .CH_Wr(RCAP2H_Wr), 
      .CL_Wr(RCAP2L_Wr), 
      .H_Wr(TH2_Wr), 
      .L_Wr(TL2_Wr), 
      .Data_In(sfr_data_out_i), 
      .Data_Out(sfr_data_in_TC2), 
      .UseR2(UseR2), 
      .UseT2(UseT2), 
      .UART_Clk(UART_Clk), 
      .F(OF2)
   ); 
   //          RXD_IsO  => RXD_IsO,
   IT51_UART uart (
      .Clk(clk), 
      .Rst_n(rst_n), 
      .UseR2(UseR2), 
      .UseT2(UseT2), 
      .BaudC2(UART_Clk), 
      .BaudC1(OF1), 
      .SC_Sel(SCON_Sel), 
      .SB_Sel(SBUF_Sel), 
      .SC_Wr(SCON_Wr), 
      .SB_Wr(SBUF_Wr), 
      .SMOD(SMOD), 
      .Data_In(sfr_data_out_i), 
      .Data_Out(sfr_data_in_UART), 
      .RXD(rxd0_in), 
      .RXD_IsO(rxd_iso),
      .RXD_O(rxd0_out), 
      .TXD(txd0), 
      .RI(RI), 
      .TI(TI)
   ); 
endmodule