key.v.bak

本程序为Verilog扫描键盘成,然后送给51单片机处理的程序.

module key(
reset_n,    //复位信号
clk,        //时钟信号
key_o,      //键盘输出
row,        //行输入
col         //列输出
);
input reset_n;
input clk;
output[15:0]key_o;    //输出寄存器
reg [15:0] key_o;
output [3:0]row;
reg [3:0] row;
input [3:0]col;

reg [3:0] key_state;      //扫描状态寄存器
always@(posedge clk)
begin
	if(!reset_n)
	begin
		key_o <=16'h00;   
		key_state<=4'h00;
		row <= 4'b1111;
	end
	else
	begin
	  //scan the key board 
	  	case(key_state)    
			0:
			begin
				row[0]<=0;  //set the ROW0 
				key_state<=1;
			end		
			1:
			begin
				key_o[3:0]<= ~col;
				row[0]<=1;
				row[1]<=0;
				key_state<=2;
			end               
			2:
			begin
				key_o[7:4]<= ~col;
				row[1]<=1;
				row[2]<=0;
				key_state<=3;
			end
			3:
			begin
				key_o[11:8]<= ~col;
				row[2]<=1;
				row[3]<=0;
				key_state<=4;
			end
			4:
			begin
				key_o[15:12]<= ~col;
				row[3]<=1;
				key_state<=5;
			end
			5:
		//idel you can set a idel in the case 
			key_state<=0;
			default:
		 	begin 
			key_state<=0;
			row <= 4'b1111;
			end
		endcase
	  end
end

endmodule