mcu.tan.rpt

本程序为Verilog扫描键盘成,然后送给51单片机处理的程序.

; N/A           ; None        ; -2.319 ns ; address     ; key_var[14]           ; clk_mcu  ;
; N/A           ; None        ; -2.588 ns ; col[2]      ; key:u1|key_o[6]       ; clk_i    ;
; N/A           ; None        ; -2.759 ns ; col[2]      ; key:u1|key_o[2]       ; clk_i    ;
; N/A           ; None        ; -2.993 ns ; address     ; key_var[15]           ; clk_mcu  ;
; N/A           ; None        ; -3.535 ns ; address     ; key_var[4]            ; clk_mcu  ;
; N/A           ; None        ; -3.535 ns ; address     ; key_var[5]            ; clk_mcu  ;
; N/A           ; None        ; -3.535 ns ; address     ; key_var[6]            ; clk_mcu  ;
; N/A           ; None        ; -3.535 ns ; address     ; key_var[7]            ; clk_mcu  ;
; N/A           ; None        ; -3.855 ns ; address     ; key_var[0]            ; clk_mcu  ;
; N/A           ; None        ; -3.855 ns ; address     ; key_var[1]            ; clk_mcu  ;
; N/A           ; None        ; -3.855 ns ; address     ; key_var[2]            ; clk_mcu  ;
; N/A           ; None        ; -3.855 ns ; address     ; key_var[3]            ; clk_mcu  ;
; N/A           ; None        ; -4.802 ns ; col[3]      ; key:u1|key_o[15]      ; clk_i    ;
; N/A           ; None        ; -4.901 ns ; col[3]      ; key:u1|key_o[11]      ; clk_i    ;
; N/A           ; None        ; -4.904 ns ; col[1]      ; key:u1|key_o[13]      ; clk_i    ;
; N/A           ; None        ; -5.034 ns ; reset_n     ; key:u1|key_state.0101 ; clk_i    ;
; N/A           ; None        ; -5.358 ns ; col[0]      ; key:u1|key_o[8]       ; clk_i    ;
; N/A           ; None        ; -5.365 ns ; col[0]      ; key:u1|key_o[4]       ; clk_i    ;
; N/A           ; None        ; -5.422 ns ; col[3]      ; key:u1|key_o[3]       ; clk_i    ;
; N/A           ; None        ; -5.464 ns ; reset_n     ; key:u1|key_state.0000 ; clk_i    ;
; N/A           ; None        ; -5.467 ns ; reset_n     ; key:u1|key_state.0010 ; clk_i    ;
; N/A           ; None        ; -5.471 ns ; reset_n     ; key:u1|key_state.0001 ; clk_i    ;
; N/A           ; None        ; -5.499 ns ; reset_n     ; key:u1|key_state.0011 ; clk_i    ;
; N/A           ; None        ; -5.510 ns ; reset_n     ; key:u1|key_state.0100 ; clk_i    ;
; N/A           ; None        ; -5.609 ns ; col[1]      ; key:u1|key_o[9]       ; clk_i    ;
; N/A           ; None        ; -5.612 ns ; col[3]      ; key:u1|key_o[7]       ; clk_i    ;
; N/A           ; None        ; -5.663 ns ; col[0]      ; key:u1|key_o[12]      ; clk_i    ;
; N/A           ; None        ; -5.767 ns ; col[0]      ; key:u1|key_o[0]       ; clk_i    ;
; N/A           ; None        ; -5.829 ns ; reset_n     ; key:u1|key_o[13]      ; clk_i    ;
; N/A           ; None        ; -5.926 ns ; col[1]      ; key:u1|key_o[1]       ; clk_i    ;
; N/A           ; None        ; -6.074 ns ; reset_n     ; key:u1|key_o[14]      ; clk_i    ;
; N/A           ; None        ; -6.128 ns ; col[1]      ; key:u1|key_o[5]       ; clk_i    ;
; N/A           ; None        ; -6.148 ns ; reset_n     ; key:u1|key_o[4]       ; clk_i    ;
; N/A           ; None        ; -6.148 ns ; reset_n     ; key:u1|key_o[5]       ; clk_i    ;
; N/A           ; None        ; -6.148 ns ; reset_n     ; key:u1|key_o[6]       ; clk_i    ;
; N/A           ; None        ; -6.148 ns ; reset_n     ; key:u1|key_o[7]       ; clk_i    ;
; N/A           ; None        ; -6.249 ns ; reset_n     ; key:u1|row[0]         ; clk_i    ;
; N/A           ; None        ; -6.249 ns ; reset_n     ; key:u1|row[1]         ; clk_i    ;
; N/A           ; None        ; -6.259 ns ; reset_n     ; key:u1|key_o[15]      ; clk_i    ;
; N/A           ; None        ; -6.285 ns ; reset_n     ; key:u1|row[2]         ; clk_i    ;
; N/A           ; None        ; -6.285 ns ; reset_n     ; key:u1|row[3]         ; clk_i    ;
; N/A           ; None        ; -6.349 ns ; reset_n     ; key:u1|key_o[10]      ; clk_i    ;
; N/A           ; None        ; -6.358 ns ; reset_n     ; key:u1|key_o[11]      ; clk_i    ;
; N/A           ; None        ; -6.534 ns ; reset_n     ; key:u1|key_o[9]       ; clk_i    ;
; N/A           ; None        ; -6.619 ns ; reset_n     ; key:u1|key_o[0]       ; clk_i    ;
; N/A           ; None        ; -6.619 ns ; reset_n     ; key:u1|key_o[1]       ; clk_i    ;
; N/A           ; None        ; -6.619 ns ; reset_n     ; key:u1|key_o[2]       ; clk_i    ;
; N/A           ; None        ; -6.619 ns ; reset_n     ; key:u1|key_o[3]       ; clk_i    ;
; N/A           ; None        ; -6.638 ns ; reset_n     ; key:u1|key_o[8]       ; clk_i    ;
; N/A           ; None        ; -6.925 ns ; reset_n     ; key:u1|key_o[12]      ; clk_i    ;
+---------------+-------------+-----------+-------------+-----------------------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 7.1 Build 156 04/30/2007 SJ Full Version
    Info: Processing started: Thu May 24 10:13:09 2007
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off mcu -c mcu --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk_mcu" is an undefined clock
    Info: Assuming node "clk_i" is an undefined clock
Info: No valid register-to-register data paths exist for clock "clk_mcu"
Info: Clock "clk_i" Internal fmax is restricted to 275.03 MHz between source register "key:u1|key_state.0100" and destination register "key:u1|key_o[12]"
    Info: fmax restricted to Clock High delay (1.818 ns) plus Clock Low delay (1.818 ns) : restricted to 3.636 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 2.274 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X9_Y10_N5; Fanout = 3; REG Node = 'key:u1|key_state.0100'
            Info: 2: + IC(0.556 ns) + CELL(0.114 ns) = 0.670 ns; Loc. = LC_X9_Y10_N7; Fanout = 4; COMB Node = 'key:u1|key_o[12]~887'
            Info: 3: + IC(0.737 ns) + CELL(0.867 ns) = 2.274 ns; Loc. = LC_X8_Y10_N3; Fanout = 1; REG Node = 'key:u1|key_o[12]'
            Info: Total cell delay = 0.981 ns ( 43.14 % )
            Info: Total interconnect delay = 1.293 ns ( 56.86 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "clk_i" to destination register is 2.768 ns
                Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_16; Fanout = 26; CLK Node = 'clk_i'
                Info: 2: + IC(0.588 ns) + CELL(0.711 ns) = 2.768 ns; Loc. = LC_X8_Y10_N3; Fanout = 1; REG Node = 'key:u1|key_o[12]'
                Info: Total cell delay = 2.180 ns ( 78.76 % )
                Info: Total interconnect delay = 0.588 ns ( 21.24 % )
            Info: - Longest clock path from clock "clk_i" to source register is 2.768 ns
                Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_16; Fanout = 26; CLK Node = 'clk_i'
                Info: 2: + IC(0.588 ns) + CELL(0.711 ns) = 2.768 ns; Loc. = LC_X9_Y10_N5; Fanout = 3; REG Node = 'key:u1|key_state.0100'
                Info: Total cell delay = 2.180 ns ( 78.76 % )
                Info: Total interconnect delay = 0.588 ns ( 21.24 % )
        Info: + Micro clock to output delay of source is 0.224 ns
        Info: + Micro setup delay of destination is 0.037 ns
Info: tsu for register "key:u1|key_o[0]" (data pin = "reset_n", clock pin = "clk_i") is 7.469 ns
    Info: + Longest pin to register delay is 10.200 ns
        Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_144; Fanout = 36; PIN Node = 'reset_n'
        Info: 2: + IC(6.189 ns) + CELL(0.590 ns) = 8.254 ns; Loc. = LC_X9_Y13_N2; Fanout = 4; COMB Node = 'key:u1|key_o~880'
        Info: 3: + IC(1.637 ns) + CELL(0.309 ns) = 10.200 ns; Loc. = LC_X11_Y11_N5; Fanout = 1; REG Node = 'key:u1|key_o[0]'
        Info: Total cell delay = 2.374 ns ( 23.27 % )
        Info: Total interconnect delay = 7.826 ns ( 76.73 % )
    Info: + Micro setup delay of destination is 0.037 ns
    Info: - Shortest clock path from clock "clk_i" to destination register is 2.768 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_16; Fanout = 26; CLK Node = 'clk_i'
        Info: 2: + IC(0.588 ns) + CELL(0.711 ns) = 2.768 ns; Loc. = LC_X11_Y11_N5; Fanout = 1; REG Node = 'key:u1|key_o[0]'
        Info: Total cell delay = 2.180 ns ( 78.76 % )
        Info: Total interconnect delay = 0.588 ns ( 21.24 % )
Info: tco from clock "clk_mcu" to destination pin "mcu_int0_o" through register "key_var[13]" is 14.203 ns
    Info: + Longest clock path from clock "clk_mcu" to source register is 6.960 ns
        Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_140; Fanout = 16; CLK Node = 'clk_mcu'
        Info: 2: + IC(4.774 ns) + CELL(0.711 ns) = 6.960 ns; Loc. = LC_X8_Y10_N4; Fanout = 2; REG Node = 'key_var[13]'
        Info: Total cell delay = 2.186 ns ( 31.41 % )
        Info: Total interconnect delay = 4.774 ns ( 68.59 % )
    Info: + Micro clock to output delay of source is 0.224 ns
    Info: + Longest register to pin delay is 7.019 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X8_Y10_N4; Fanout = 2; REG Node = 'key_var[13]'
        Info: 2: + IC(1.223 ns) + CELL(0.590 ns) = 1.813 ns; Loc. = LC_X10_Y10_N2; Fanout = 1; COMB Node = 'Equal0~149'
        Info: 3: + IC(1.213 ns) + CELL(0.590 ns) = 3.616 ns; Loc. = LC_X9_Y12_N2; Fanout = 1; COMB Node = 'Equal0~150'
        Info: 4: + IC(1.295 ns) + CELL(2.108 ns) = 7.019 ns; Loc. = PIN_132; Fanout = 0; PIN Node = 'mcu_int0_o'
        Info: Total cell delay = 3.288 ns ( 46.84 % )
        Info: Total interconnect delay = 3.731 ns ( 53.16 % )
Info: Longest tpd from source pin "address" to destination pin "mcu_data[6]" is 13.604 ns
    Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 10; PIN Node = 'address'
    Info: 2: + IC(7.283 ns) + CELL(0.590 ns) = 9.342 ns; Loc. = LC_X9_Y11_N2; Fanout = 1; COMB Node = 'mcu_data~110'
    Info: 3: + IC(2.138 ns) + CELL(2.124 ns) = 13.604 ns; Loc. = PIN_4; Fanout = 0; PIN Node = 'mcu_data[6]'
    Info: Total cell delay = 4.183 ns ( 30.75 % )
    Info: Total interconnect delay = 9.421 ns ( 69.25 % )
Info: th for register "key_var[3]" (data pin = "wr_n", clock pin = "clk_mcu") is -0.194 ns
    Info: + Longest clock path from clock "clk_mcu" to destination register is 6.960 ns
        Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_140; Fanout = 16; CLK Node = 'clk_mcu'
        Info: 2: + IC(4.774 ns) + CELL(0.711 ns) = 6.960 ns; Loc. = LC_X8_Y12_N2; Fanout = 2; REG Node = 'key_var[3]'
        Info: Total cell delay = 2.186 ns ( 31.41 % )
        Info: Total interconnect delay = 4.774 ns ( 68.59 % )
    Info: + Micro hold delay of destination is 0.015 ns
    Info: - Shortest pin to register delay is 7.169 ns
        Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_134; Fanout = 18; PIN Node = 'wr_n'
        Info: 2: + IC(5.216 ns) + CELL(0.478 ns) = 7.169 ns; Loc. = LC_X8_Y12_N2; Fanout = 2; REG Node = 'key_var[3]'
        Info: Total cell delay = 1.953 ns ( 27.24 % )
        Info: Total interconnect delay = 5.216 ns ( 72.76 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning
    Info: Allocated 106 megabytes of memory during processing
    Info: Processing ended: Thu May 24 10:13:10 2007
    Info: Elapsed time: 00:00:01