mcu.tan.qmsg

本程序为Verilog扫描键盘成,然后送给51单片机处理的程序.

{ "Info" "ITDB_FULL_TPD_RESULT" "address mcu_data\[6\] 13.604 ns Longest " "Info: Longest tpd from source pin \"address\" to destination pin \"mcu_data\[6\]\" is 13.604 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns address 1 PIN PIN_28 10 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 10; PIN Node = 'address'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { address } "NODE_NAME" } } { "top.v" "" { Text "E:/project/zhm1101/program/Verilog/li cheng/top.v" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(7.283 ns) + CELL(0.590 ns) 9.342 ns mcu_data~110 2 COMB LC_X9_Y11_N2 1 " "Info: 2: + IC(7.283 ns) + CELL(0.590 ns) = 9.342 ns; Loc. = LC_X9_Y11_N2; Fanout = 1; COMB Node = 'mcu_data~110'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "7.873 ns" { address mcu_data~110 } "NODE_NAME" } } { "top.v" "" { Text "E:/project/zhm1101/program/Verilog/li cheng/top.v" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.138 ns) + CELL(2.124 ns) 13.604 ns mcu_data\[6\] 3 PIN PIN_4 0 " "Info: 3: + IC(2.138 ns) + CELL(2.124 ns) = 13.604 ns; Loc. = PIN_4; Fanout = 0; PIN Node = 'mcu_data\[6\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "4.262 ns" { mcu_data~110 mcu_data[6] } "NODE_NAME" } } { "top.v" "" { Text "E:/project/zhm1101/program/Verilog/li cheng/top.v" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.183 ns ( 30.75 % ) " "Info: Total cell delay = 4.183 ns ( 30.75 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "9.421 ns ( 69.25 % ) " "Info: Total interconnect delay = 9.421 ns ( 69.25 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "13.604 ns" { address mcu_data~110 mcu_data[6] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "13.604 ns" { address address~out0 mcu_data~110 mcu_data[6] } { 0.000ns 0.000ns 7.283ns 2.138ns } { 0.000ns 1.469ns 0.590ns 2.124ns } "" } }  } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0 "" 0}
{ "Info" "ITDB_TH_RESULT" "key_var\[3\] wr_n clk_mcu -0.194 ns register " "Info: th for register \"key_var\[3\]\" (data pin = \"wr_n\", clock pin = \"clk_mcu\") is -0.194 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_mcu destination 6.960 ns + Longest register " "Info: + Longest clock path from clock \"clk_mcu\" to destination register is 6.960 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns clk_mcu 1 CLK PIN_140 16 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_140; Fanout = 16; CLK Node = 'clk_mcu'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk_mcu } "NODE_NAME" } } { "top.v" "" { Text "E:/project/zhm1101/program/Verilog/li cheng/top.v" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(4.774 ns) + CELL(0.711 ns) 6.960 ns key_var\[3\] 2 REG LC_X8_Y12_N2 2 " "Info: 2: + IC(4.774 ns) + CELL(0.711 ns) = 6.960 ns; Loc. = LC_X8_Y12_N2; Fanout = 2; REG Node = 'key_var\[3\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "5.485 ns" { clk_mcu key_var[3] } "NODE_NAME" } } { "top.v" "" { Text "E:/project/zhm1101/program/Verilog/li cheng/top.v" 47 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.186 ns ( 31.41 % ) " "Info: Total cell delay = 2.186 ns ( 31.41 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.774 ns ( 68.59 % ) " "Info: Total interconnect delay = 4.774 ns ( 68.59 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "6.960 ns" { clk_mcu key_var[3] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "6.960 ns" { clk_mcu clk_mcu~out0 key_var[3] } { 0.000ns 0.000ns 4.774ns } { 0.000ns 1.475ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "0.015 ns + " "Info: + Micro hold delay of destination is 0.015 ns" {  } { { "top.v" "" { Text "E:/project/zhm1101/program/Verilog/li cheng/top.v" 47 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.169 ns - Shortest pin register " "Info: - Shortest pin to register delay is 7.169 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns wr_n 1 PIN PIN_134 18 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_134; Fanout = 18; PIN Node = 'wr_n'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { wr_n } "NODE_NAME" } } { "top.v" "" { Text "E:/project/zhm1101/program/Verilog/li cheng/top.v" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(5.216 ns) + CELL(0.478 ns) 7.169 ns key_var\[3\] 2 REG LC_X8_Y12_N2 2 " "Info: 2: + IC(5.216 ns) + CELL(0.478 ns) = 7.169 ns; Loc. = LC_X8_Y12_N2; Fanout = 2; REG Node = 'key_var\[3\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "5.694 ns" { wr_n key_var[3] } "NODE_NAME" } } { "top.v" "" { Text "E:/project/zhm1101/program/Verilog/li cheng/top.v" 47 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.953 ns ( 27.24 % ) " "Info: Total cell delay = 1.953 ns ( 27.24 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.216 ns ( 72.76 % ) " "Info: Total interconnect delay = 5.216 ns ( 72.76 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "7.169 ns" { wr_n key_var[3] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "7.169 ns" { wr_n wr_n~out0 key_var[3] } { 0.000ns 0.000ns 5.216ns } { 0.000ns 1.475ns 0.478ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "6.960 ns" { clk_mcu key_var[3] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "6.960 ns" { clk_mcu clk_mcu~out0 key_var[3] } { 0.000ns 0.000ns 4.774ns } { 0.000ns 1.475ns 0.711ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "7.169 ns" { wr_n key_var[3] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "7.169 ns" { wr_n wr_n~out0 key_var[3] } { 0.000ns 0.000ns 5.216ns } { 0.000ns 1.475ns 0.478ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "106 " "Info: Allocated 106 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Thu May 24 10:13:10 2007 " "Info: Processing ended: Thu May 24 10:13:10 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}