mcu.map.rpt

本程序为Verilog扫描键盘成,然后送给51单片机处理的程序.

;     -- 3 input functions                    ; 12      ;
;     -- 2 input functions                    ; 15      ;
;     -- 1 input functions                    ; 16      ;
;     -- 0 input functions                    ; 0       ;
;                                             ;         ;
; Logic elements by mode                      ;         ;
;     -- normal mode                          ; 66      ;
;     -- arithmetic mode                      ; 0       ;
;     -- qfbk mode                            ; 0       ;
;     -- register cascade mode                ; 0       ;
;     -- synchronous clear/load mode          ; 20      ;
;     -- asynchronous clear/load mode         ; 0       ;
;                                             ;         ;
; Total registers                             ; 42      ;
; I/O pins                                    ; 25      ;
; Maximum fan-out node                        ; reset_n ;
; Maximum fan-out                             ; 36      ;
; Total fan-out                               ; 289     ;
; Average fan-out                             ; 3.18    ;
+---------------------------------------------+---------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                                   ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+--------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ; Library Name ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+--------------+
; |mcu                       ; 66 (32)     ; 42           ; 0           ; 25   ; 0            ; 24 (16)      ; 0 (0)             ; 42 (16)          ; 0 (0)           ; 0 (0)      ; |mcu                ; work         ;
;    |key:u1|                ; 34 (34)     ; 26           ; 0           ; 0    ; 0            ; 8 (8)        ; 0 (0)             ; 26 (26)          ; 0 (0)           ; 0 (0)      ; |mcu|key:u1         ; work         ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


Encoding Type:  One-Hot
+----------------------------------------------------------------------------------------------------------------------+
; State Machine - |mcu|key:u1|key_state                                                                                ;
+----------------+----------------+----------------+----------------+----------------+----------------+----------------+
; Name           ; key_state.0101 ; key_state.0001 ; key_state.0010 ; key_state.0011 ; key_state.0100 ; key_state.0000 ;
+----------------+----------------+----------------+----------------+----------------+----------------+----------------+
; key_state.0000 ; 0              ; 0              ; 0              ; 0              ; 0              ; 0              ;
; key_state.0100 ; 0              ; 0              ; 0              ; 0              ; 1              ; 1              ;
; key_state.0011 ; 0              ; 0              ; 0              ; 1              ; 0              ; 1              ;
; key_state.0010 ; 0              ; 0              ; 1              ; 0              ; 0              ; 1              ;
; key_state.0001 ; 0              ; 1              ; 0              ; 0              ; 0              ; 1              ;
; key_state.0101 ; 1              ; 0              ; 0              ; 0              ; 0              ; 1              ;
+----------------+----------------+----------------+----------------+----------------+----------------+----------------+


+------------------------------------------------------------+
; Registers Removed During Synthesis                         ;
+---------------------------------------+--------------------+
; Register name                         ; Reason for Removal ;
+---------------------------------------+--------------------+
; u1/key_state~25                       ; Lost fanout        ;
; u1/key_state~26                       ; Lost fanout        ;
; u1/key_state~27                       ; Lost fanout        ;
; u1/key_state~28                       ; Lost fanout        ;
; Total Number of Removed Registers = 4 ;                    ;
+---------------------------------------+--------------------+


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 42    ;
; Number of registers using Synchronous Clear  ; 16    ;
; Number of registers using Synchronous Load   ; 4     ;
; Number of registers using Asynchronous Clear ; 0     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 32    ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                           ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; 3:1                ; 4 bits    ; 8 LEs         ; 4 LEs                ; 4 LEs                  ; Yes        ; |mcu|key:u1|key_o[12]      ;
; 3:1                ; 4 bits    ; 8 LEs         ; 4 LEs                ; 4 LEs                  ; Yes        ; |mcu|key:u1|key_o[8]       ;
; 3:1                ; 4 bits    ; 8 LEs         ; 4 LEs                ; 4 LEs                  ; Yes        ; |mcu|key:u1|key_o[4]       ;
; 3:1                ; 4 bits    ; 8 LEs         ; 4 LEs                ; 4 LEs                  ; Yes        ; |mcu|key:u1|key_o[3]       ;
; 4:1                ; 8 bits    ; 16 LEs        ; 16 LEs               ; 0 LEs                  ; Yes        ; |mcu|key_var[12]           ;
; 4:1                ; 8 bits    ; 16 LEs        ; 16 LEs               ; 0 LEs                  ; Yes        ; |mcu|key_var[2]            ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 7.1 Build 156 04/30/2007 SJ Full Version
    Info: Processing started: Thu May 24 10:12:50 2007
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off mcu -c mcu
Info: Found 1 design units, including 1 entities, in source file top.v
    Info: Found entity 1: mcu
Info: Elaborating entity "mcu" for the top level hierarchy
Warning (10230): Verilog HDL assignment warning at top.v(29): truncated value with size 32 to match size of target (1)
Warning (10034): Output port "beep" at top.v(24) has no driver
Warning: Using design file key.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: key
Info: Elaborating entity "key" for hierarchy "key:u1"
Info: State machine "|mcu|key:u1|key_state" contains 6 states
Info: Selected Auto state machine encoding method for state machine "|mcu|key:u1|key_state"
Info: Encoding result for state machine "|mcu|key:u1|key_state"
    Info: Completed encoding using 6 state bits
        Info: Encoded state bit "key:u1|key_state.0101"
        Info: Encoded state bit "key:u1|key_state.0001"
        Info: Encoded state bit "key:u1|key_state.0010"
        Info: Encoded state bit "key:u1|key_state.0011"
        Info: Encoded state bit "key:u1|key_state.0100"
        Info: Encoded state bit "key:u1|key_state.0000"
    Info: State "|mcu|key:u1|key_state.0000" uses code string "000000"
    Info: State "|mcu|key:u1|key_state.0100" uses code string "000011"
    Info: State "|mcu|key:u1|key_state.0011" uses code string "000101"
    Info: State "|mcu|key:u1|key_state.0010" uses code string "001001"
    Info: State "|mcu|key:u1|key_state.0001" uses code string "010001"
    Info: State "|mcu|key:u1|key_state.0101" uses code string "100001"
Warning: Output pins are stuck at VCC or GND
    Warning: Pin "beep" stuck at GND
Info: 4 registers lost all their fanouts during netlist optimizations. The first 4 are displayed below.
    Info: Register "u1/key_state~25" lost all its fanouts during netlist optimizations.
    Info: Register "u1/key_state~26" lost all its fanouts during netlist optimizations.
    Info: Register "u1/key_state~27" lost all its fanouts during netlist optimizations.
    Info: Register "u1/key_state~28" lost all its fanouts during netlist optimizations.
Info: Implemented 91 device resources after synthesis - the final resource count might be different
    Info: Implemented 11 input pins
    Info: Implemented 6 output pins
    Info: Implemented 8 bidirectional pins
    Info: Implemented 66 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 5 warnings
    Info: Allocated 136 megabytes of memory during processing
    Info: Processing ended: Thu May 24 10:12:53 2007
    Info: Elapsed time: 00:00:03