top.v

本程序为Verilog扫描键盘成,然后送给51单片机处理的程序.

module top(
cpld_cs,
address,
clk_i,
wr_n,
rd_n,
mcu_data,
mcu_int0_o,
reset_n,
row,
col
);
input reset_n;
input cpld_cs;
input address;
input clk_i;
input wr_n;
input rd_n;
inout [7:0]mcu_data;
output mcu_int0_o;
reg [15:0] key_var;
output [3:0]row;
input [3:0]col;

assign mcu_int0_o = (key_var != 16'h00)?0:1; //低电平中断

//call key module and get the value from key
wire [15:0] key_o;
key u1(
.reset_n(reset_n),
.clk(clk_i),
.key_o(key_o),
.row(row),
.col(col)

);

//--------mcu read the value 
assign mcu_data =( (cpld_cs==1) && (rd_n ==0) )?(address ==0 )?key_var[7:0]:key_var[15:8]:8'hzz;

// write the reg and clean the int
always@(posedge clk_i) 
begin
if(~reset_n)
	begin
	key_var <= 16'h00;
	end
else
begin 
	if((cpld_cs==1)&&(wr_n ==0) )
	begin
		case(address)
		0:
		begin
		  	key_var[7:0]<= mcu_data;
		end
		1:
		begin
			key_var[15:8]<= mcu_data;
		end
		endcase
	end
	else
	begin
	 key_var <= key_o;
	end
end
end
endmodule