prev_cmp_mcu.qmsg

本程序为Verilog扫描键盘成,然后送给51单片机处理的程序.

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.1 Build 156 04/30/2007 SJ Full Version " "Info: Version 7.1 Build 156 04/30/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu May 24 10:04:11 2007 " "Info: Processing started: Thu May 24 10:04:11 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off mcu -c mcu " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off mcu -c mcu" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "top.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file top.v" { { "Info" "ISGN_ENTITY_NAME" "1 mcu " "Info: Found entity 1: mcu" {  } { { "top.v" "" { Text "E:/project/zhm1101/program/Verilog/li cheng/top.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "mcu " "Info: Elaborating entity \"mcu\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 top.v(29) " "Warning (10230): Verilog HDL assignment warning at top.v(29): truncated value with size 32 to match size of target (1)" {  } { { "top.v" "" { Text "E:/project/zhm1101/program/Verilog/li cheng/top.v" 29 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "beep top.v(24) " "Warning (10034): Output port \"beep\" at top.v(24) has no driver" {  } { { "top.v" "" { Text "E:/project/zhm1101/program/Verilog/li cheng/top.v" 24 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "" 0}
{ "Warning" "WSGN_SEARCH_FILE" "key.v 1 1 " "Warning: Using design file key.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 key " "Info: Found entity 1: key" {  } { { "key.v" "" { Text "E:/project/zhm1101/program/Verilog/li cheng/key.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "key key:u1 " "Info: Elaborating entity \"key\" for hierarchy \"key:u1\"" {  } { { "top.v" "u1" { Text "E:/project/zhm1101/program/Verilog/li cheng/top.v" 41 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "IOPT_SMP_MACHINE_PREPROCESS_STAT_NO_BITS" "\|mcu\|key:u1\|key_state 6 " "Info: State machine \"\|mcu\|key:u1\|key_state\" contains 6 states" {  } { { "key.v" "" { Text "E:/project/zhm1101/program/Verilog/li cheng/key.v" 16 -1 0 } }  } 0 0 "State machine \"%1!s!\" contains %2!d! states" 0 0 "" 0}
{ "Info" "IOPT_SMP_MACHINE_REPORT_PROCESSOR" "Auto \|mcu\|key:u1\|key_state " "Info: Selected Auto state machine encoding method for state machine \"\|mcu\|key:u1\|key_state\"" {  } { { "key.v" "" { Text "E:/project/zhm1101/program/Verilog/li cheng/key.v" 16 -1 0 } }  } 0 0 "Selected %1!s! state machine encoding method for state machine \"%2!s!\"" 0 0 "" 0}
{ "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_HEADER" "\|mcu\|key:u1\|key_state " "Info: Encoding result for state machine \"\|mcu\|key:u1\|key_state\"" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS_HEADER" "6 " "Info: Completed encoding using 6 state bits" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "key:u1\|key_state.0101 " "Info: Encoded state bit \"key:u1\|key_state.0101\"" {  } { { "key.v" "" { Text "E:/project/zhm1101/program/Verilog/li cheng/key.v" 16 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "key:u1\|key_state.0001 " "Info: Encoded state bit \"key:u1\|key_state.0001\"" {  } { { "key.v" "" { Text "E:/project/zhm1101/program/Verilog/li cheng/key.v" 16 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "key:u1\|key_state.0010 " "Info: Encoded state bit \"key:u1\|key_state.0010\"" {  } { { "key.v" "" { Text "E:/project/zhm1101/program/Verilog/li cheng/key.v" 16 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "key:u1\|key_state.0011 " "Info: Encoded state bit \"key:u1\|key_state.0011\"" {  } { { "key.v" "" { Text "E:/project/zhm1101/program/Verilog/li cheng/key.v" 16 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "key:u1\|key_state.0100 " "Info: Encoded state bit \"key:u1\|key_state.0100\"" {  } { { "key.v" "" { Text "E:/project/zhm1101/program/Verilog/li cheng/key.v" 16 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "key:u1\|key_state.0000 " "Info: Encoded state bit \"key:u1\|key_state.0000\"" {  } { { "key.v" "" { Text "E:/project/zhm1101/program/Verilog/li cheng/key.v" 16 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0 "" 0}  } {  } 0 0 "Completed encoding using %1!d! state bits" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|mcu\|key:u1\|key_state.0000 000000 " "Info: State \"\|mcu\|key:u1\|key_state.0000\" uses code string \"000000\"" {  } { { "key.v" "" { Text "E:/project/zhm1101/program/Verilog/li cheng/key.v" 16 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|mcu\|key:u1\|key_state.0100 000011 " "Info: State \"\|mcu\|key:u1\|key_state.0100\" uses code string \"000011\"" {  } { { "key.v" "" { Text "E:/project/zhm1101/program/Verilog/li cheng/key.v" 16 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|mcu\|key:u1\|key_state.0011 000101 " "Info: State \"\|mcu\|key:u1\|key_state.0011\" uses code string \"000101\"" {  } { { "key.v" "" { Text "E:/project/zhm1101/program/Verilog/li cheng/key.v" 16 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|mcu\|key:u1\|key_state.0010 001001 " "Info: State \"\|mcu\|key:u1\|key_state.0010\" uses code string \"001001\"" {  } { { "key.v" "" { Text "E:/project/zhm1101/program/Verilog/li cheng/key.v" 16 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|mcu\|key:u1\|key_state.0001 010001 " "Info: State \"\|mcu\|key:u1\|key_state.0001\" uses code string \"010001\"" {  } { { "key.v" "" { Text "E:/project/zhm1101/program/Verilog/li cheng/key.v" 16 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|mcu\|key:u1\|key_state.0101 100001 " "Info: State \"\|mcu\|key:u1\|key_state.0101\" uses code string \"100001\"" {  } { { "key.v" "" { Text "E:/project/zhm1101/program/Verilog/li cheng/key.v" 16 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0 "" 0}  } { { "key.v" "" { Text "E:/project/zhm1101/program/Verilog/li cheng/key.v" 16 -1 0 } }  } 0 0 "Encoding result for state machine \"%1!s!\"" 0 0 "" 0}
{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "beep GND " "Warning: Pin \"beep\" stuck at GND" {  } { { "top.v" "" { Text "E:/project/zhm1101/program/Verilog/li cheng/top.v" 24 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0 "" 0}  } {  } 0 0 "Output pins are stuck at VCC or GND" 0 0 "" 0}
{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "4 4 " "Info: 4 registers lost all their fanouts during netlist optimizations. The first 4 are displayed below." { { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "u1/key_state~25 " "Info: Register \"u1/key_state~25\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "u1/key_state~26 " "Info: Register \"u1/key_state~26\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "u1/key_state~27 " "Info: Register \"u1/key_state~27\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "u1/key_state~28 " "Info: Register \"u1/key_state~28\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0}  } {  } 0 0 "%1!d! registers lost all their fanouts during netlist optimizations. The first %2!d! are displayed below." 0 0 "" 0}
{ "Info" "ICUT_CUT_TM_SUMMARY" "91 " "Info: Implemented 91 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "11 " "Info: Implemented 11 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_OPINS" "6 " "Info: Implemented 6 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_BIDIRS" "8 " "Info: Implemented 8 bidirectional pins" {  } {  } 0 0 "Implemented %1!d! bidirectional pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_LCELLS" "66 " "Info: Implemented 66 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0}