decdor_38.vhd

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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity decdor_38 is
    Port ( clk : in std_logic;
           rst : in std_logic;
           a : in std_logic_vector(2 downto 0);
           data_out : out std_logic_vector(7 downto 0));
end decdor_38;

architecture Behavioral of decdor_38 is

signal data_mid:std_logic_vector(7 downto 0):="00000000";
signal mix:std_logic_vector(2 downto 0);

begin
--mix<=a&b&c;
mix<=a(0)&a(1)&a(2);

reset:process(clk)
        begin
        if(rst='1') then
           data_out<="00000000";
        else
           data_out<=data_mid; 
        end if;
        end process;

data_p: process(clk)

        begin

          if(clk'event and clk='1') then

             case mix is
               when "000" => data_mid<="00000001";
               when "001" => data_mid<="00000010";
               when "010" => data_mid<="00000100";
               when "011" => data_mid<="00001000";
               when "100" => data_mid<="00010000";
               when "101" => data_mid<="00100000";
               when "110" => data_mid<="01000000";
               when "111" => data_mid<="10000000";
	       when others=>	data_mid<="XXXXXXXX";
              end case;
          end if;
          end process;


end Behavioral;