shft_reg.vhd

来自「用VHDL编的移位寄存器,具有置位,清零,装载,方向功能.~」· VHDL 代码 · 共 53 行

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;


Entity shft_reg is
Port (
DIR : in std_logic;
CLK : in std_logic;
CLR : in std_logic;
SET : in std_logic;
CE : in std_logic;
LOAD : in std_logic;
SI : in std_logic;
DATA : in std_logic_vector ( 3 downto 0);
Data_out : out std_logic_vector ( 3 downto 0)
);
End entity;


Architecture shft_reg_arch of shft_reg is
Signal TEMP_data_out : std_logic_vector ( 3 downto 0);
Begin

Process(CLK)
begin
if rising_edge(CLK) then
if CE = '1' then
if CLR = '1' then
TEMP_data_out <= "0000";
elsif SET = '1' then
TEMP_data_out <= "1111";
elsif  LOAD = '1' then
TEMP_data_out <= DATA;
Else
If  DIR = '1' then
TEMP_data_out <=SI & TEMP_data_out( 3 downto 1);
else
if  DIR = '1' then
TEMP_data_out <= TEMP_data_out( 2 downto 0) & SI;
end if;
end if;
end if;
end if;
end if;
end Process;

data_out <= TEMP_data_out;

end Architecture;