zhutaiji.vhd

能够检测各种状态

Library IEEE;
Use IEEE.std_logic_1164.all;

Entity zhutaiji is 
     port ( xi,clock,reset :in BIT;
		   zo :out BIT);
End zhutaiji;

Architecture behav of zhutaiji is
     type state_type is (s1, s2,s3,s4,s5, s6, s7,s8);
     signal present_state, next_state : state_type;
Begin
  seq: process (clock,reset) is 
     begin
            if (reset='1') then	present_state<=s1;
	    elsif  (clock'event and clock='1')  then
				present_state <= next_state;
            end if ;
      end process seq ;

  com: process ( xi, present_state ) 
     begin
			zo <= '0';
			case present_state is
                 when s1 =>
                 if ( xi = '1' ) then
                        next_state<=s2;
                 else
                        next_state<=s1;
				 end if;
				 when s2=>
                 if ( xi = '1' ) then
                        next_state<=s3;
                 else
                        next_state<=s1;
				 end if;
				 when s3 =>
                 if ( xi = '1' ) then
                        next_state<=s4;
                 else
                        next_state<=s1;
				 end if;
				 when s4 =>
                 if ( xi = '0' ) then
                        next_state<=s5;
                 else
                        next_state<=s4;
				 end if;
				 when s5 =>
                 if ( xi = '0' ) then
                        next_state<=s6;
                 else
                        next_state<=s2;
				 end if;
				 when s6 =>
                 if ( xi = '1' ) then
                        next_state<=s7;
                 else
                        next_state<=s1;
				 end if;
				 when s7=>
                 if ( xi = '0' ) then
                        next_state<=s8;
                 else
                        next_state<=s3;
				 end if;
				 when s8 =>
				 zo <= '1';
                 if ( xi = '1' ) then
                        next_state<=s2;
                 else
                        next_state<=s1;
                 end if ;
			end case;
	End process com;
End behav;