zhutaiji.tan.qmsg

能够检测各种状态

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "clock register register present_state.s4 present_state.s5 422.12 MHz Internal " "Info: Clock \"clock\" Internal fmax is restricted to 422.12 MHz between source register \"present_state.s4\" and destination register \"present_state.s5\"" { { "Info" "ITDB_CLOCK_RATE" "clock 2.369 ns " "Info: fmax restricted to clock pin edge rate 2.369 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.966 ns + Longest register register " "Info: + Longest register to register delay is 0.966 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns present_state.s4 1 REG LC_X31_Y30_N8 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X31_Y30_N8; Fanout = 3; REG Node = 'present_state.s4'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "zhutaiji" "UNKNOWN" "V1" "F:/VHDL2/project/8/db/8.quartus_db" { Floorplan "F:/VHDL2/project/8/" "" "" { present_state.s4 } "NODE_NAME" } "" } } { "zhutaiji.vhd" "" { Text "F:/VHDL2/project/8/zhutaiji.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.427 ns) + CELL(0.539 ns) 0.966 ns present_state.s5 2 REG LC_X31_Y30_N9 3 " "Info: 2: + IC(0.427 ns) + CELL(0.539 ns) = 0.966 ns; Loc. = LC_X31_Y30_N9; Fanout = 3; REG Node = 'present_state.s5'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "zhutaiji" "UNKNOWN" "V1" "F:/VHDL2/project/8/db/8.quartus_db" { Floorplan "F:/VHDL2/project/8/" "" "0.966 ns" { present_state.s4 present_state.s5 } "NODE_NAME" } "" } } { "zhutaiji.vhd" "" { Text "F:/VHDL2/project/8/zhutaiji.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.539 ns ( 55.80 % ) " "Info: Total cell delay = 0.539 ns ( 55.80 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.427 ns ( 44.20 % ) " "Info: Total interconnect delay = 0.427 ns ( 44.20 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "zhutaiji" "UNKNOWN" "V1" "F:/VHDL2/project/8/db/8.quartus_db" { Floorplan "F:/VHDL2/project/8/" "" "0.966 ns" { present_state.s4 present_state.s5 } "NODE_NAME" } "" } } { "e:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus51/bin/Technology_Viewer.qrui" "0.966 ns" { present_state.s4 present_state.s5 } { 0.000ns 0.427ns } { 0.000ns 0.539ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock destination 2.808 ns + Shortest register " "Info: + Shortest clock path from clock \"clock\" to destination register is 2.808 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.725 ns) 0.725 ns clock 1 CLK PIN_L2 8 " "Info: 1: + IC(0.000 ns) + CELL(0.725 ns) = 0.725 ns; Loc. = PIN_L2; Fanout = 8; CLK Node = 'clock'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "zhutaiji" "UNKNOWN" "V1" "F:/VHDL2/project/8/db/8.quartus_db" { Floorplan "F:/VHDL2/project/8/" "" "" { clock } "NODE_NAME" } "" } } { "zhutaiji.vhd" "" { Text "F:/VHDL2/project/8/zhutaiji.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.541 ns) + CELL(0.542 ns) 2.808 ns present_state.s5 2 REG LC_X31_Y30_N9 3 " "Info: 2: + IC(1.541 ns) + CELL(0.542 ns) = 2.808 ns; Loc. = LC_X31_Y30_N9; Fanout = 3; REG Node = 'present_state.s5'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "zhutaiji" "UNKNOWN" "V1" "F:/VHDL2/project/8/db/8.quartus_db" { Floorplan "F:/VHDL2/project/8/" "" "2.083 ns" { clock present_state.s5 } "NODE_NAME" } "" } } { "zhutaiji.vhd" "" { Text "F:/VHDL2/project/8/zhutaiji.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.267 ns ( 45.12 % ) " "Info: Total cell delay = 1.267 ns ( 45.12 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.541 ns ( 54.88 % ) " "Info: Total interconnect delay = 1.541 ns ( 54.88 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "zhutaiji" "UNKNOWN" "V1" "F:/VHDL2/project/8/db/8.quartus_db" { Floorplan "F:/VHDL2/project/8/" "" "2.808 ns" { clock present_state.s5 } "NODE_NAME" } "" } } { "e:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus51/bin/Technology_Viewer.qrui" "2.808 ns" { clock clock~out0 present_state.s5 } { 0.000ns 0.000ns 1.541ns } { 0.000ns 0.725ns 0.542ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock source 2.808 ns - Longest register " "Info: - Longest clock path from clock \"clock\" to source register is 2.808 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.725 ns) 0.725 ns clock 1 CLK PIN_L2 8 " "Info: 1: + IC(0.000 ns) + CELL(0.725 ns) = 0.725 ns; Loc. = PIN_L2; Fanout = 8; CLK Node = 'clock'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "zhutaiji" "UNKNOWN" "V1" "F:/VHDL2/project/8/db/8.quartus_db" { Floorplan "F:/VHDL2/project/8/" "" "" { clock } "NODE_NAME" } "" } } { "zhutaiji.vhd" "" { Text "F:/VHDL2/project/8/zhutaiji.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.541 ns) + CELL(0.542 ns) 2.808 ns present_state.s4 2 REG LC_X31_Y30_N8 3 " "Info: 2: + IC(1.541 ns) + CELL(0.542 ns) = 2.808 ns; Loc. = LC_X31_Y30_N8; Fanout = 3; REG Node = 'present_state.s4'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "zhutaiji" "UNKNOWN" "V1" "F:/VHDL2/project/8/db/8.quartus_db" { Floorplan "F:/VHDL2/project/8/" "" "2.083 ns" { clock present_state.s4 } "NODE_NAME" } "" } } { "zhutaiji.vhd" "" { Text "F:/VHDL2/project/8/zhutaiji.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.267 ns ( 45.12 % ) " "Info: Total cell delay = 1.267 ns ( 45.12 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.541 ns ( 54.88 % ) " "Info: Total interconnect delay = 1.541 ns ( 54.88 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "zhutaiji" "UNKNOWN" "V1" "F:/VHDL2/project/8/db/8.quartus_db" { Floorplan "F:/VHDL2/project/8/" "" "2.808 ns" { clock present_state.s4 } "NODE_NAME" } "" } } { "e:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus51/bin/Technology_Viewer.qrui" "2.808 ns" { clock clock~out0 present_state.s4 } { 0.000ns 0.000ns 1.541ns } { 0.000ns 0.725ns 0.542ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "zhutaiji" "UNKNOWN" "V1" "F:/VHDL2/project/8/db/8.quartus_db" { Floorplan "F:/VHDL2/project/8/" "" "2.808 ns" { clock present_state.s5 } "NODE_NAME" } "" } } { "e:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus51/bin/Technology_Viewer.qrui" "2.808 ns" { clock clock~out0 present_state.s5 } { 0.000ns 0.000ns 1.541ns } { 0.000ns 0.725ns 0.542ns } } } { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "zhutaiji" "UNKNOWN" "V1" "F:/VHDL2/project/8/db/8.quartus_db" { Floorplan "F:/VHDL2/project/8/" "" "2.808 ns" { clock present_state.s4 } "NODE_NAME" } "" } } { "e:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus51/bin/Technology_Viewer.qrui" "2.808 ns" { clock clock~out0 present_state.s4 } { 0.000ns 0.000ns 1.541ns } { 0.000ns 0.725ns 0.542ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.156 ns + " "Info: + Micro clock to output delay of source is 0.156 ns" {  } { { "zhutaiji.vhd" "" { Text "F:/VHDL2/project/8/zhutaiji.vhd" 15 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.010 ns + " "Info: + Micro setup delay of destination is 0.010 ns" {  } { { "zhutaiji.vhd" "" { Text "F:/VHDL2/project/8/zhutaiji.vhd" 15 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "zhutaiji" "UNKNOWN" "V1" "F:/VHDL2/project/8/db/8.quartus_db" { Floorplan "F:/VHDL2/project/8/" "" "0.966 ns" { present_state.s4 present_state.s5 } "NODE_NAME" } "" } } { "e:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus51/bin/Technology_Viewer.qrui" "0.966 ns" { present_state.s4 present_state.s5 } { 0.000ns 0.427ns } { 0.000ns 0.539ns } } } { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "zhutaiji" "UNKNOWN" "V1" "F:/VHDL2/project/8/db/8.quartus_db" { Floorplan "F:/VHDL2/project/8/" "" "2.808 ns" { clock present_state.s5 } "NODE_NAME" } "" } } { "e:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus51/bin/Technology_Viewer.qrui" "2.808 ns" { clock clock~out0 present_state.s5 } { 0.000ns 0.000ns 1.541ns } { 0.000ns 0.725ns 0.542ns } } } { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "zhutaiji" "UNKNOWN" "V1" "F:/VHDL2/project/8/db/8.quartus_db" { Floorplan "F:/VHDL2/project/8/" "" "2.808 ns" { clock present_state.s4 } "NODE_NAME" } "" } } { "e:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus51/bin/Technology_Viewer.qrui" "2.808 ns" { clock clock~out0 present_state.s4 } { 0.000ns 0.000ns 1.541ns } { 0.000ns 0.725ns 0.542ns } } }  } 0 0 "fmax restricted to %1!s! pin edge rate %2!s!. Expand message to see actual delay path." 0 0}  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "zhutaiji" "UNKNOWN" "V1" "F:/VHDL2/project/8/db/8.quartus_db" { Floorplan "F:/VHDL2/project/8/" "" "" { present_state.s5 } "NODE_NAME" } "" } } { "e:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus51/bin/Technology_Viewer.qrui" "" { present_state.s5 } {  } {  } } } { "zhutaiji.vhd" "" { Text "F:/VHDL2/project/8/zhutaiji.vhd" 15 -1 0 } }  } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0}
{ "Info" "ITDB_TSU_RESULT" "present_state.s8 xi clock 2.616 ns register " "Info: tsu for register \"present_state.s8\" (data pin = \"xi\", clock pin = \"clock\") is 2.616 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.414 ns + Longest pin register " "Info: + Longest pin to register delay is 5.414 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.087 ns) 1.087 ns xi 1 PIN PIN_K10 8 " "Info: 1: + IC(0.000 ns) + CELL(1.087 ns) = 1.087 ns; Loc. = PIN_K10; Fanout = 8; PIN Node = 'xi'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "zhutaiji" "UNKNOWN" "V1" "F:/VHDL2/project/8/db/8.quartus_db" { Floorplan "F:/VHDL2/project/8/" "" "" { xi } "NODE_NAME" } "" } } { "zhutaiji.vhd" "" { Text "F:/VHDL2/project/8/zhutaiji.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.788 ns) + CELL(0.539 ns) 5.414 ns present_state.s8 2 REG LC_X31_Y30_N4 2 " "Info: 2: + IC(3.788 ns) + CELL(0.539 ns) = 5.414 ns; Loc. = LC_X31_Y30_N4; Fanout = 2; REG Node = 'present_state.s8'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "zhutaiji" "UNKNOWN" "V1" "F:/VHDL2/project/8/db/8.quartus_db" { Floorplan "F:/VHDL2/project/8/" "" "4.327 ns" { xi present_state.s8 } "NODE_NAME" } "" } } { "zhutaiji.vhd" "" { Text "F:/VHDL2/project/8/zhutaiji.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.626 ns ( 30.03 % ) " "Info: Total cell delay = 1.626 ns ( 30.03 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.788 ns ( 69.97 % ) " "Info: Total interconnect delay = 3.788 ns ( 69.97 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "zhutaiji" "UNKNOWN" "V1" "F:/VHDL2/project/8/db/8.quartus_db" { Floorplan "F:/VHDL2/project/8/" "" "5.414 ns" { xi present_state.s8 } "NODE_NAME" } "" } } { "e:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus51/bin/Technology_Viewer.qrui" "5.414 ns" { xi xi~out0 present_state.s8 } { 0.000ns 0.000ns 3.788ns } { 0.000ns 1.087ns 0.539ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.010 ns + " "Info: + Micro setup delay of destination is 0.010 ns" {  } { { "zhutaiji.vhd" "" { Text "F:/VHDL2/project/8/zhutaiji.vhd" 15 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock destination 2.808 ns - Shortest register " "Info: - Shortest clock path from clock \"clock\" to destination register is 2.808 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.725 ns) 0.725 ns clock 1 CLK PIN_L2 8 " "Info: 1: + IC(0.000 ns) + CELL(0.725 ns) = 0.725 ns; Loc. = PIN_L2; Fanout = 8; CLK Node = 'clock'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "zhutaiji" "UNKNOWN" "V1" "F:/VHDL2/project/8/db/8.quartus_db" { Floorplan "F:/VHDL2/project/8/" "" "" { clock } "NODE_NAME" } "" } } { "zhutaiji.vhd" "" { Text "F:/VHDL2/project/8/zhutaiji.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.541 ns) + CELL(0.542 ns) 2.808 ns present_state.s8 2 REG LC_X31_Y30_N4 2 " "Info: 2: + IC(1.541 ns) + CELL(0.542 ns) = 2.808 ns; Loc. = LC_X31_Y30_N4; Fanout = 2; REG Node = 'present_state.s8'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "zhutaiji" "UNKNOWN" "V1" "F:/VHDL2/project/8/db/8.quartus_db" { Floorplan "F:/VHDL2/project/8/" "" "2.083 ns" { clock present_state.s8 } "NODE_NAME" } "" } } { "zhutaiji.vhd" "" { Text "F:/VHDL2/project/8/zhutaiji.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.267 ns ( 45.12 % ) " "Info: Total cell delay = 1.267 ns ( 45.12 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.541 ns ( 54.88 % ) " "Info: Total interconnect delay = 1.541 ns ( 54.88 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "zhutaiji" "UNKNOWN" "V1" "F:/VHDL2/project/8/db/8.quartus_db" { Floorplan "F:/VHDL2/project/8/" "" "2.808 ns" { clock present_state.s8 } "NODE_NAME" } "" } } { "e:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus51/bin/Technology_Viewer.qrui" "2.808 ns" { clock clock~out0 present_state.s8 } { 0.000ns 0.000ns 1.541ns } { 0.000ns 0.725ns 0.542ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "zhutaiji" "UNKNOWN" "V1" "F:/VHDL2/project/8/db/8.quartus_db" { Floorplan "F:/VHDL2/project/8/" "" "5.414 ns" { xi present_state.s8 } "NODE_NAME" } "" } } { "e:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus51/bin/Technology_Viewer.qrui" "5.414 ns" { xi xi~out0 present_state.s8 } { 0.000ns 0.000ns 3.788ns } { 0.000ns 1.087ns 0.539ns } } } { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "zhutaiji" "UNKNOWN" "V1" "F:/VHDL2/project/8/db/8.quartus_db" { Floorplan "F:/VHDL2/project/8/" "" "2.808 ns" { clock present_state.s8 } "NODE_NAME" } "" } } { "e:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus51/bin/Technology_Viewer.qrui" "2.808 ns" { clock clock~out0 present_state.s8 } { 0.000ns 0.000ns 1.541ns } { 0.000ns 0.725ns 0.542ns } } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clock zo present_state.s8 6.530 ns register " "Info: tco from clock \"clock\" to destination pin \"zo\" through register \"present_state.s8\" is 6.530 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock source 2.808 ns + Longest register " "Info: + Longest clock path from clock \"clock\" to source register is 2.808 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.725 ns) 0.725 ns clock 1 CLK PIN_L2 8 " "Info: 1: + IC(0.000 ns) + CELL(0.725 ns) = 0.725 ns; Loc. = PIN_L2; Fanout = 8; CLK Node = 'clock'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "zhutaiji" "UNKNOWN" "V1" "F:/VHDL2/project/8/db/8.quartus_db" { Floorplan "F:/VHDL2/project/8/" "" "" { clock } "NODE_NAME" } "" } } { "zhutaiji.vhd" "" { Text "F:/VHDL2/project/8/zhutaiji.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.541 ns) + CELL(0.542 ns) 2.808 ns present_state.s8 2 REG LC_X31_Y30_N4 2 " "Info: 2: + IC(1.541 ns) + CELL(0.542 ns) = 2.808 ns; Loc. = LC_X31_Y30_N4; Fanout = 2; REG Node = 'present_state.s8'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "zhutaiji" "UNKNOWN" "V1" "F:/VHDL2/project/8/db/8.quartus_db" { Floorplan "F:/VHDL2/project/8/" "" "2.083 ns" { clock present_state.s8 } "NODE_NAME" } "" } } { "zhutaiji.vhd" "" { Text "F:/VHDL2/project/8/zhutaiji.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.267 ns ( 45.12 % ) " "Info: Total cell delay = 1.267 ns ( 45.12 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.541 ns ( 54.88 % ) " "Info: Total interconnect delay = 1.541 ns ( 54.88 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "zhutaiji" "UNKNOWN" "V1" "F:/VHDL2/project/8/db/8.quartus_db" { Floorplan "F:/VHDL2/project/8/" "" "2.808 ns" { clock present_state.s8 } "NODE_NAME" } "" } } { "e:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus51/bin/Technology_Viewer.qrui" "2.808 ns" { clock clock~out0 present_state.s8 } { 0.000ns 0.000ns 1.541ns } { 0.000ns 0.725ns 0.542ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.156 ns + " "Info: + Micro clock to output delay of source is 0.156 ns" {  } { { "zhutaiji.vhd" "" { Text "F:/VHDL2/project/8/zhutaiji.vhd" 15 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.566 ns + Longest register pin " "Info: + Longest register to pin delay is 3.566 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns present_state.s8 1 REG LC_X31_Y30_N4 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X31_Y30_N4; Fanout = 2; REG Node = 'present_state.s8'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "zhutaiji" "UNKNOWN" "V1" "F:/VHDL2/project/8/db/8.quartus_db" { Floorplan "F:/VHDL2/project/8/" "" "" { present_state.s8 } "NODE_NAME" } "" } } { "zhutaiji.vhd" "" { Text "F:/VHDL2/project/8/zhutaiji.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.162 ns) + CELL(2.404 ns) 3.566 ns zo 2 PIN PIN_G9 0 " "Info: 2: + IC(1.162 ns) + CELL(2.404 ns) = 3.566 ns; Loc. = PIN_G9; Fanout = 0; PIN Node = 'zo'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "zhutaiji" "UNKNOWN" "V1" "F:/VHDL2/project/8/db/8.quartus_db" { Floorplan "F:/VHDL2/project/8/" "" "3.566 ns" { present_state.s8 zo } "NODE_NAME" } "" } } { "zhutaiji.vhd" "" { Text "F:/VHDL2/project/8/zhutaiji.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.404 ns ( 67.41 % ) " "Info: Total cell delay = 2.404 ns ( 67.41 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.162 ns ( 32.59 % ) " "Info: Total interconnect delay = 1.162 ns ( 32.59 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "zhutaiji" "UNKNOWN" "V1" "F:/VHDL2/project/8/db/8.quartus_db" { Floorplan "F:/VHDL2/project/8/" "" "3.566 ns" { present_state.s8 zo } "NODE_NAME" } "" } } { "e:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus51/bin/Technology_Viewer.qrui" "3.566 ns" { present_state.s8 zo } { 0.000ns 1.162ns } { 0.000ns 2.404ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "zhutaiji" "UNKNOWN" "V1" "F:/VHDL2/project/8/db/8.quartus_db" { Floorplan "F:/VHDL2/project/8/" "" "2.808 ns" { clock present_state.s8 } "NODE_NAME" } "" } } { "e:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus51/bin/Technology_Viewer.qrui" "2.808 ns" { clock clock~out0 present_state.s8 } { 0.000ns 0.000ns 1.541ns } { 0.000ns 0.725ns 0.542ns } } } { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "zhutaiji" "UNKNOWN" "V1" "F:/VHDL2/project/8/db/8.quartus_db" { Floorplan "F:/VHDL2/project/8/" "" "3.566 ns" { present_state.s8 zo } "NODE_NAME" } "" } } { "e:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus51/bin/Technology_Viewer.qrui" "3.566 ns" { present_state.s8 zo } { 0.000ns 1.162ns } { 0.000ns 2.404ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "present_state.s2 xi clock -2.272 ns register " "Info: th for register \"present_state.s2\" (data pin = \"xi\", clock pin = \"clock\") is -2.272 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock destination 2.808 ns + Longest register " "Info: + Longest clock path from clock \"clock\" to destination register is 2.808 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.725 ns) 0.725 ns clock 1 CLK PIN_L2 8 " "Info: 1: + IC(0.000 ns) + CELL(0.725 ns) = 0.725 ns; Loc. = PIN_L2; Fanout = 8; CLK Node = 'clock'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "zhutaiji" "UNKNOWN" "V1" "F:/VHDL2/project/8/db/8.quartus_db" { Floorplan "F:/VHDL2/project/8/" "" "" { clock } "NODE_NAME" } "" } } { "zhutaiji.vhd" "" { Text "F:/VHDL2/project/8/zhutaiji.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.541 ns) + CELL(0.542 ns) 2.808 ns present_state.s2 2 REG LC_X31_Y30_N6 1 " "Info: 2: + IC(1.541 ns) + CELL(0.542 ns) = 2.808 ns; Loc. = LC_X31_Y30_N6; Fanout = 1; REG Node = 'present_state.s2'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "zhutaiji" "UNKNOWN" "V1" "F:/VHDL2/project/8/db/8.quartus_db" { Floorplan "F:/VHDL2/project/8/" "" "2.083 ns" { clock present_state.s2 } "NODE_NAME" } "" } } { "zhutaiji.vhd" "" { Text "F:/VHDL2/project/8/zhutaiji.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.267 ns ( 45.12 % ) " "Info: Total cell delay = 1.267 ns ( 45.12 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.541 ns ( 54.88 % ) " "Info: Total interconnect delay = 1.541 ns ( 54.88 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "zhutaiji" "UNKNOWN" "V1" "F:/VHDL2/project/8/db/8.quartus_db" { Floorplan "F:/VHDL2/project/8/" "" "2.808 ns" { clock present_state.s2 } "NODE_NAME" } "" } } { "e:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus51/bin/Technology_Viewer.qrui" "2.808 ns" { clock clock~out0 present_state.s2 } { 0.000ns 0.000ns 1.541ns } { 0.000ns 0.725ns 0.542ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.100 ns + " "Info: + Micro hold delay of destination is 0.100 ns" {  } { { "zhutaiji.vhd" "" { Text "F:/VHDL2/project/8/zhutaiji.vhd" 15 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.180 ns - Shortest pin register " "Info: - Shortest pin to register delay is 5.180 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.087 ns) 1.087 ns xi 1 PIN PIN_K10 8 " "Info: 1: + IC(0.000 ns) + CELL(1.087 ns) = 1.087 ns; Loc. = PIN_K10; Fanout = 8; PIN Node = 'xi'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "zhutaiji" "UNKNOWN" "V1" "F:/VHDL2/project/8/db/8.quartus_db" { Floorplan "F:/VHDL2/project/8/" "" "" { xi } "NODE_NAME" } "" } } { "zhutaiji.vhd" "" { Text "F:/VHDL2/project/8/zhutaiji.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.774 ns) + CELL(0.319 ns) 5.180 ns present_state.s2 2 REG LC_X31_Y30_N6 1 " "Info: 2: + IC(3.774 ns) + CELL(0.319 ns) = 5.180 ns; Loc. = LC_X31_Y30_N6; Fanout = 1; REG Node = 'present_state.s2'" {  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "zhutaiji" "UNKNOWN" "V1" "F:/VHDL2/project/8/db/8.quartus_db" { Floorplan "F:/VHDL2/project/8/" "" "4.093 ns" { xi present_state.s2 } "NODE_NAME" } "" } } { "zhutaiji.vhd" "" { Text "F:/VHDL2/project/8/zhutaiji.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.406 ns ( 27.14 % ) " "Info: Total cell delay = 1.406 ns ( 27.14 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.774 ns ( 72.86 % ) " "Info: Total interconnect delay = 3.774 ns ( 72.86 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "zhutaiji" "UNKNOWN" "V1" "F:/VHDL2/project/8/db/8.quartus_db" { Floorplan "F:/VHDL2/project/8/" "" "5.180 ns" { xi present_state.s2 } "NODE_NAME" } "" } } { "e:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus51/bin/Technology_Viewer.qrui" "5.180 ns" { xi xi~out0 present_state.s2 } { 0.000ns 0.000ns 3.774ns } { 0.000ns 1.087ns 0.319ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "zhutaiji" "UNKNOWN" "V1" "F:/VHDL2/project/8/db/8.quartus_db" { Floorplan "F:/VHDL2/project/8/" "" "2.808 ns" { clock present_state.s2 } "NODE_NAME" } "" } } { "e:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus51/bin/Technology_Viewer.qrui" "2.808 ns" { clock clock~out0 present_state.s2 } { 0.000ns 0.000ns 1.541ns } { 0.000ns 0.725ns 0.542ns } } } { "e:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "e:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "zhutaiji" "UNKNOWN" "V1" "F:/VHDL2/project/8/db/8.quartus_db" { Floorplan "F:/VHDL2/project/8/" "" "5.180 ns" { xi present_state.s2 } "NODE_NAME" } "" } } { "e:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus51/bin/Technology_Viewer.qrui" "5.180 ns" { xi xi~out0 present_state.s2 } { 0.000ns 0.000ns 3.774ns } { 0.000ns 1.087ns 0.319ns } } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}