zhutaiji.tan.rpt

能够检测各种状态

; Slack ; Required tsu ; Actual tsu ; From ; To               ; To Clock ;
+-------+--------------+------------+------+------------------+----------+
; N/A   ; None         ; 2.616 ns   ; xi   ; present_state.s8 ; clock    ;
; N/A   ; None         ; 2.616 ns   ; xi   ; present_state.s7 ; clock    ;
; N/A   ; None         ; 2.605 ns   ; xi   ; present_state.s3 ; clock    ;
; N/A   ; None         ; 2.391 ns   ; xi   ; present_state.s1 ; clock    ;
; N/A   ; None         ; 2.389 ns   ; xi   ; present_state.s5 ; clock    ;
; N/A   ; None         ; 2.386 ns   ; xi   ; present_state.s4 ; clock    ;
; N/A   ; None         ; 2.384 ns   ; xi   ; present_state.s6 ; clock    ;
; N/A   ; None         ; 2.382 ns   ; xi   ; present_state.s2 ; clock    ;
+-------+--------------+------------+------+------------------+----------+


+------------------------------------------------------------------------+
; tco                                                                    ;
+-------+--------------+------------+------------------+----+------------+
; Slack ; Required tco ; Actual tco ; From             ; To ; From Clock ;
+-------+--------------+------------+------------------+----+------------+
; N/A   ; None         ; 6.530 ns   ; present_state.s8 ; zo ; clock      ;
+-------+--------------+------------+------------------+----+------------+


+------------------------------------------------------------------------------+
; th                                                                           ;
+---------------+-------------+-----------+------+------------------+----------+
; Minimum Slack ; Required th ; Actual th ; From ; To               ; To Clock ;
+---------------+-------------+-----------+------+------------------+----------+
; N/A           ; None        ; -2.272 ns ; xi   ; present_state.s2 ; clock    ;
; N/A           ; None        ; -2.274 ns ; xi   ; present_state.s6 ; clock    ;
; N/A           ; None        ; -2.276 ns ; xi   ; present_state.s4 ; clock    ;
; N/A           ; None        ; -2.279 ns ; xi   ; present_state.s5 ; clock    ;
; N/A           ; None        ; -2.281 ns ; xi   ; present_state.s1 ; clock    ;
; N/A           ; None        ; -2.495 ns ; xi   ; present_state.s3 ; clock    ;
; N/A           ; None        ; -2.506 ns ; xi   ; present_state.s8 ; clock    ;
; N/A           ; None        ; -2.506 ns ; xi   ; present_state.s7 ; clock    ;
+---------------+-------------+-----------+------+------------------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 5.1 Build 176 10/26/2005 SJ Full Version
    Info: Processing started: Wed May 23 12:33:34 2007
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off 8 -c zhutaiji --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clock" is an undefined clock
Info: Clock "clock" Internal fmax is restricted to 422.12 MHz between source register "present_state.s4" and destination register "present_state.s5"
    Info: fmax restricted to clock pin edge rate 2.369 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 0.966 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X31_Y30_N8; Fanout = 3; REG Node = 'present_state.s4'
            Info: 2: + IC(0.427 ns) + CELL(0.539 ns) = 0.966 ns; Loc. = LC_X31_Y30_N9; Fanout = 3; REG Node = 'present_state.s5'
            Info: Total cell delay = 0.539 ns ( 55.80 % )
            Info: Total interconnect delay = 0.427 ns ( 44.20 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "clock" to destination register is 2.808 ns
                Info: 1: + IC(0.000 ns) + CELL(0.725 ns) = 0.725 ns; Loc. = PIN_L2; Fanout = 8; CLK Node = 'clock'
                Info: 2: + IC(1.541 ns) + CELL(0.542 ns) = 2.808 ns; Loc. = LC_X31_Y30_N9; Fanout = 3; REG Node = 'present_state.s5'
                Info: Total cell delay = 1.267 ns ( 45.12 % )
                Info: Total interconnect delay = 1.541 ns ( 54.88 % )
            Info: - Longest clock path from clock "clock" to source register is 2.808 ns
                Info: 1: + IC(0.000 ns) + CELL(0.725 ns) = 0.725 ns; Loc. = PIN_L2; Fanout = 8; CLK Node = 'clock'
                Info: 2: + IC(1.541 ns) + CELL(0.542 ns) = 2.808 ns; Loc. = LC_X31_Y30_N8; Fanout = 3; REG Node = 'present_state.s4'
                Info: Total cell delay = 1.267 ns ( 45.12 % )
                Info: Total interconnect delay = 1.541 ns ( 54.88 % )
        Info: + Micro clock to output delay of source is 0.156 ns
        Info: + Micro setup delay of destination is 0.010 ns
Info: tsu for register "present_state.s8" (data pin = "xi", clock pin = "clock") is 2.616 ns
    Info: + Longest pin to register delay is 5.414 ns
        Info: 1: + IC(0.000 ns) + CELL(1.087 ns) = 1.087 ns; Loc. = PIN_K10; Fanout = 8; PIN Node = 'xi'
        Info: 2: + IC(3.788 ns) + CELL(0.539 ns) = 5.414 ns; Loc. = LC_X31_Y30_N4; Fanout = 2; REG Node = 'present_state.s8'
        Info: Total cell delay = 1.626 ns ( 30.03 % )
        Info: Total interconnect delay = 3.788 ns ( 69.97 % )
    Info: + Micro setup delay of destination is 0.010 ns
    Info: - Shortest clock path from clock "clock" to destination register is 2.808 ns
        Info: 1: + IC(0.000 ns) + CELL(0.725 ns) = 0.725 ns; Loc. = PIN_L2; Fanout = 8; CLK Node = 'clock'
        Info: 2: + IC(1.541 ns) + CELL(0.542 ns) = 2.808 ns; Loc. = LC_X31_Y30_N4; Fanout = 2; REG Node = 'present_state.s8'
        Info: Total cell delay = 1.267 ns ( 45.12 % )
        Info: Total interconnect delay = 1.541 ns ( 54.88 % )
Info: tco from clock "clock" to destination pin "zo" through register "present_state.s8" is 6.530 ns
    Info: + Longest clock path from clock "clock" to source register is 2.808 ns
        Info: 1: + IC(0.000 ns) + CELL(0.725 ns) = 0.725 ns; Loc. = PIN_L2; Fanout = 8; CLK Node = 'clock'
        Info: 2: + IC(1.541 ns) + CELL(0.542 ns) = 2.808 ns; Loc. = LC_X31_Y30_N4; Fanout = 2; REG Node = 'present_state.s8'
        Info: Total cell delay = 1.267 ns ( 45.12 % )
        Info: Total interconnect delay = 1.541 ns ( 54.88 % )
    Info: + Micro clock to output delay of source is 0.156 ns
    Info: + Longest register to pin delay is 3.566 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X31_Y30_N4; Fanout = 2; REG Node = 'present_state.s8'
        Info: 2: + IC(1.162 ns) + CELL(2.404 ns) = 3.566 ns; Loc. = PIN_G9; Fanout = 0; PIN Node = 'zo'
        Info: Total cell delay = 2.404 ns ( 67.41 % )
        Info: Total interconnect delay = 1.162 ns ( 32.59 % )
Info: th for register "present_state.s2" (data pin = "xi", clock pin = "clock") is -2.272 ns
    Info: + Longest clock path from clock "clock" to destination register is 2.808 ns
        Info: 1: + IC(0.000 ns) + CELL(0.725 ns) = 0.725 ns; Loc. = PIN_L2; Fanout = 8; CLK Node = 'clock'
        Info: 2: + IC(1.541 ns) + CELL(0.542 ns) = 2.808 ns; Loc. = LC_X31_Y30_N6; Fanout = 1; REG Node = 'present_state.s2'
        Info: Total cell delay = 1.267 ns ( 45.12 % )
        Info: Total interconnect delay = 1.541 ns ( 54.88 % )
    Info: + Micro hold delay of destination is 0.100 ns
    Info: - Shortest pin to register delay is 5.180 ns
        Info: 1: + IC(0.000 ns) + CELL(1.087 ns) = 1.087 ns; Loc. = PIN_K10; Fanout = 8; PIN Node = 'xi'
        Info: 2: + IC(3.774 ns) + CELL(0.319 ns) = 5.180 ns; Loc. = LC_X31_Y30_N6; Fanout = 1; REG Node = 'present_state.s2'
        Info: Total cell delay = 1.406 ns ( 27.14 % )
        Info: Total interconnect delay = 3.774 ns ( 72.86 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Wed May 23 12:33:34 2007
    Info: Elapsed time: 00:00:01