tester_behaviour.vhd

关于8086的软核fpga代码

-------------------------------------------------------------------------------
--                                                                           --
--  CPU86 - VHDL CPU8088 IP core                                             --
--  Copyright (C) 2005 HT-LAB 												 --
--                                                                           --
--  Contact : mailto:[e-mail]					                     --
--  Web: http://www.ht-lab.com												 --
--                                                                           --
-------------------------------------------------------------------------------
--																			 --
--  This library is free software; you can redistribute it and/or            --
--  modify it under the terms of the GNU Lesser General Public               --
--  License as published by the Free Software Foundation; either             --
--  version 2.1 of the License, or (at your option) any later version.       --
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--  This library is distributed in the hope that it will be useful,          --
--  but WITHOUT ANY WARRANTY; without even the implied warranty of           --
--  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU        --
--  Lesser General Public License for more details.                          --
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--  Full details of the license can be found in the file "copying.txt".      --
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--  You should have received a copy of the GNU Lesser General Public         --
--  License along with this library; if not, write to the Free Software      --
--  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA  --
--                                                                           --
-------------------------------------------------------------------------------
--
-- VHDL Entity web_example.tester.behaviour
--
-- Created: by - Hans 27/08/2005
--
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE ieee.std_logic_unsigned.all;
LIBRARY std;
USE std.textio.all;

USE work.utils.all;

ENTITY tester IS
   PORT( 
      cpu_resetn : OUT    std_logic;
      rxenable   : OUT    std_logic;
      txcmd      : OUT    std_logic;
      user_pbx   : OUT    std_logic_vector (3 DOWNTO 0);
      clk_s      : BUFFER std_logic:='0';
      resoutn    : BUFFER std_logic;
      txenable   : BUFFER std_logic
   );
END tester ;


ARCHITECTURE behaviour OF tester IS

component uarttx
	port (
		clk    : in     std_logic ;
		enable : in     std_logic ;          	-- 1 x bit_rate transmit clock enable
		resetn : in     std_logic ;
		dbus   : in     std_logic_vector (7 downto 0); -- input to txshift register
		tdre   : out    std_logic ;
		wrn    : in     std_logic ;
		tx     : out    std_logic);
end component;

constant DIVIDER_c	: std_logic_vector(7 downto 0):="00110100"; -- 52, baudrate divider
signal 	 divtx_s 	: std_logic_vector(3 downto 0);
signal 	 divreg_s 	: std_logic_vector(7 downto 0);
signal 	 divcnt_s 	: std_logic_vector(7 downto 0);
signal 	 rxclk16_s 	: std_logic;

signal 	 tdre_s	 	: std_logic;
signal 	 wrn_s	 	: std_logic;
signal 	 char_s		: std_logic_vector(7 downto 0);


BEGIN

	clk_s <= not clk_s after 15.2941175 ns;		-- 32.xxxMHz

	process
		variable L   : line;

		procedure write_to_uart (char_in  : IN character) is   
		begin
			char_s <=to_std_logic_vector(char_in);
			wait until rising_edge(clk_s);
			wrn_s	<= '0';							
			wait until rising_edge(clk_s);
			wrn_s	<=	'1';
			wait until rising_edge(clk_s);
			wait until rising_edge(tdre_s);
		end;

		begin
			resoutn		<= '0';
			cpu_resetn	<= '0';
			wrn_s		<= '1';					-- Active low write strobe to TX UART
			char_s 		<= (others => '1');					
			user_pbx 	<= "HHHH";
			--user_pbx 	<= "HHH0"; 				-- Enable Hardware Monitor, also change 
												-- ROM file from ROM.HEX to ROMSS.HEX
			wait for 100 ns;
			resoutn		<= '1';
			cpu_resetn	<= '1';
			wait for 25.1 ms;					-- wait for > prompt before issuing commands

			write_to_uart('R');					
--			write(L,string'("WR UART : R"));
--			writeline(output,L);
			
			wait for 47 ms;						-- wait for > prompt before issuing commands

			write_to_uart('D');					-- Issue Fill Memory command
			write_to_uart('M');
			write_to_uart('0');
			write_to_uart('1');
			write_to_uart('0');
			write_to_uart('0');
			wait for 1 ms;
			write_to_uart('0');
			write_to_uart('1');
			write_to_uart('2');
			write_to_uart('4');

--			write(L,string'("WR UART : DM 0100-0124"));
--			writeline(output,L);

			wait for 50 ms;						-- wait for > prompt before issuing commands

			wait;
	end process; 
	
	------------------------------------------------------------------------------
	-- 8 bits divider
	-- Generate rxenable clock
	------------------------------------------------------------------------------
	process (clk_s,resoutn)         				-- First divider
	   begin
	       if (resoutn='0') then                     
	          divcnt_s <= (others => '0');   
	          rxclk16_s <= '0';              	-- Receive clock (x16, pulse)               
	       elsif (rising_edge(clk_s)) then 
	         if divcnt_s=DIVIDER_c then
	            divcnt_s <= (others => '0');    
	            rxclk16_s <= '1';       
	         else                                  
	            rxclk16_s <= '0';
	            divcnt_s <= divcnt_s + '1';  
	         end if;
	       end if;   
	end process;

	rxenable <= rxclk16_s;

	------------------------------------------------------------------------------
	-- divider by 16 
	-- rxclk16/16=txclk
	------------------------------------------------------------------------------
	process (clk_s,resoutn)                             
	   begin
	        if (resoutn='0') then                     
	           divtx_s <= (others => '0');   
	        elsif (rising_edge(clk_s)) then 
	           if rxclk16_s='1' then
	               divtx_s <= divtx_s + '1';
				   if divtx_s="0000" then
					  txenable <= '1';
				   end if;	
			   else 
			   	   txenable <= '0';
			   end if;   
	        end if;   
	end process;
   
	------------------------------------------------------------------------------
	-- TX Uart 
	------------------------------------------------------------------------------
	I0 : uarttx
	      port map (
	         clk    => clk_s,
	         enable => txenable,
	         resetn => resoutn,
	         dbus   => char_s,
	         tdre   => tdre_s,
	         wrn    => wrn_s,
	         tx     => txcmd
	      );

END ARCHITECTURE behaviour;