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constant TESTI2AX0 : std_logic_vector(7 downto 0) := X"A8";
constant TESTI2AX1 : std_logic_vector(7 downto 0) := X"A9";
-----------------------------------------------------------------------------
-- NOT/TEST F6/F7 Shared Instructions
-- TEST regfield=000
-- NOT regfield=010
-- MUL regfield=100
-- IMUL regfield=101
-- DIV regfield=110
-- IDIV regfield=111
-----------------------------------------------------------------------------
constant F6INSTR : std_logic_vector(7 downto 0) := X"F6"; -- Byte
constant F7INSTR : std_logic_vector(7 downto 0) := X"F7"; -- Word
-----------------------------------------------------------------------------
-- Carry Flag CLC/CMC/STC
-----------------------------------------------------------------------------
constant CLC : std_logic_vector(7 downto 0) := X"F8";
constant CMC : std_logic_vector(7 downto 0) := X"F5";
constant STC : std_logic_vector(7 downto 0) := X"F9";
constant CLD : std_logic_vector(7 downto 0) := X"FC";
constant STDx : std_logic_vector(7 downto 0) := X"FD"; -- Strange Problem, were is STD defined?
constant CLI : std_logic_vector(7 downto 0) := X"FA";
constant STI : std_logic_vector(7 downto 0) := X"FB";
-----------------------------------------------------------------------------
-- 8080 Instruction LAHF/SAHF
-----------------------------------------------------------------------------
constant LAHF : std_logic_vector(7 downto 0) := X"9F";
constant SAHF : std_logic_vector(7 downto 0) := X"9E";
-----------------------------------------------------------------------------
-- Conditional Jumps Jxxx
-----------------------------------------------------------------------------
constant JZ : std_logic_vector(7 downto 0) := X"74";
constant JL : std_logic_vector(7 downto 0) := X"7C";
constant JLE : std_logic_vector(7 downto 0) := X"7E";
constant JB : std_logic_vector(7 downto 0) := X"72";
constant JBE : std_logic_vector(7 downto 0) := X"76";
constant JP : std_logic_vector(7 downto 0) := X"7A";
constant JO : std_logic_vector(7 downto 0) := X"70";
constant JS : std_logic_vector(7 downto 0) := X"78";
constant JNE : std_logic_vector(7 downto 0) := X"75";
constant JNL : std_logic_vector(7 downto 0) := X"7D";
constant JNLE : std_logic_vector(7 downto 0) := X"7F";
constant JNB : std_logic_vector(7 downto 0) := X"73";
constant JNBE : std_logic_vector(7 downto 0) := X"77";
constant JNP : std_logic_vector(7 downto 0) := X"7B";
constant JNO : std_logic_vector(7 downto 0) := X"71";
constant JNS : std_logic_vector(7 downto 0) := X"79";
constant JMPS : std_logic_vector(7 downto 0) := X"EB"; -- Short Jump within segment , SignExt DISPL
constant JMP : std_logic_vector(7 downto 0) := X"E9"; -- Long Jump within segment, No SignExt DISPL
constant JMPDIS : std_logic_vector(7 downto 0) := X"EA"; -- Jump Inter Segment (CS:IP given)
-----------------------------------------------------------------------------
-- Push/Pop Flags
-----------------------------------------------------------------------------
constant PUSHF : std_logic_vector(7 downto 0) := X"9C";
constant POPF : std_logic_vector(7 downto 0) := X"9D";
-----------------------------------------------------------------------------
-- PUSH Register
-----------------------------------------------------------------------------
constant PUSHAX : std_logic_vector(7 downto 0) := X"50";
constant PUSHCX : std_logic_vector(7 downto 0) := X"51";
constant PUSHDX : std_logic_vector(7 downto 0) := X"52";
constant PUSHBX : std_logic_vector(7 downto 0) := X"53";
constant PUSHSP : std_logic_vector(7 downto 0) := X"54";
constant PUSHBP : std_logic_vector(7 downto 0) := X"55";
constant PUSHSI : std_logic_vector(7 downto 0) := X"56";
constant PUSHDI : std_logic_vector(7 downto 0) := X"57";
constant PUSHES : std_logic_vector(7 downto 0) := X"06";
constant PUSHCS : std_logic_vector(7 downto 0) := X"0E";
constant PUSHSS : std_logic_vector(7 downto 0) := X"16";
constant PUSHDS : std_logic_vector(7 downto 0) := X"1E";
-----------------------------------------------------------------------------
-- Pop Register
-----------------------------------------------------------------------------
constant POPAX : std_logic_vector(7 downto 0) := X"58";
constant POPCX : std_logic_vector(7 downto 0) := X"59";
constant POPDX : std_logic_vector(7 downto 0) := X"5A";
constant POPBX : std_logic_vector(7 downto 0) := X"5B";
constant POPSP : std_logic_vector(7 downto 0) := X"5C";
constant POPBP : std_logic_vector(7 downto 0) := X"5D";
constant POPSI : std_logic_vector(7 downto 0) := X"5E";
constant POPDI : std_logic_vector(7 downto 0) := X"5F";
constant POPES : std_logic_vector(7 downto 0) := X"07";
--constant POPCS : std_logic_vector(7 downto 0) := X"1F"; -- Illegal
constant POPSS : std_logic_vector(7 downto 0) := X"17";
constant POPDS : std_logic_vector(7 downto 0) := X"1F";
constant POPRM : std_logic_vector(7 downto 0) := X"8F";
-----------------------------------------------------------------------------
-- Exchange Register
-----------------------------------------------------------------------------
constant XCHGW : std_logic_vector(7 downto 0) := X"86";
constant XCHGB : std_logic_vector(7 downto 0) := X"87";
constant XCHGAX : std_logic_vector(7 downto 0) := X"90";
constant XCHGCX : std_logic_vector(7 downto 0) := X"91";
constant XCHGDX : std_logic_vector(7 downto 0) := X"92";
constant XCHGBX : std_logic_vector(7 downto 0) := X"93";
constant XCHGSP : std_logic_vector(7 downto 0) := X"94";
constant XCHGBP : std_logic_vector(7 downto 0) := X"95";
constant XCHGSI : std_logic_vector(7 downto 0) := X"96";
constant XCHGDI : std_logic_vector(7 downto 0) := X"97";
-----------------------------------------------------------------------------
-- Load Effective Address
-----------------------------------------------------------------------------
constant LEA : std_logic_vector(7 downto 0) := X"8D";
constant LDS : std_logic_vector(7 downto 0) := X"C5";
constant LES : std_logic_vector(7 downto 0) := X"C4";
-----------------------------------------------------------------------------
-- Convert Instructions
-----------------------------------------------------------------------------
constant CBW : std_logic_vector(7 downto 0) := X"98";
constant CWD : std_logic_vector(7 downto 0) := X"99";
constant AAS : std_logic_vector(7 downto 0) := X"3F";
constant DAS : std_logic_vector(7 downto 0) := X"2F";
constant AAA : std_logic_vector(7 downto 0) := X"37";
constant DAA : std_logic_vector(7 downto 0) := X"27";
constant AAM : std_logic_vector(7 downto 0) := X"D4";
constant AAD : std_logic_vector(7 downto 0) := X"D5";
constant XLAT : std_logic_vector(7 downto 0) := X"D7";
-----------------------------------------------------------------------------
-- Misc Instructions
-----------------------------------------------------------------------------
constant NOP : std_logic_vector(7 downto 0) := X"90"; -- No Operation
constant LOCKBUS : std_logic_vector(7 downto 0) := X"F0"; -- Assert /LOCK signal
constant WAITx : std_logic_vector(7 downto 0) := X"9B"; -- WAIT is not implemented, result in NOP
constant HLT : std_logic_vector(7 downto 0) := X"F4"; -- Halt Instruction, wait NMI, INTR, Reset
-----------------------------------------------------------------------------
-- Loop Instructions
-----------------------------------------------------------------------------
constant LOOPCX : std_logic_vector(7 downto 0) := X"E2";
constant LOOPZ : std_logic_vector(7 downto 0) := X"E1";
constant LOOPNZ : std_logic_vector(7 downto 0) := X"E0";
constant JCXZ : std_logic_vector(7 downto 0) := X"E3";
-----------------------------------------------------------------------------
-- CALL Instructions
-----------------------------------------------------------------------------
constant CALL : std_logic_vector(7 downto 0) := X"E8"; -- Direct within Segment
constant CALLDIS : std_logic_vector(7 downto 0) := X"9A"; -- Direct Inter Segment
-----------------------------------------------------------------------------
-- RET Instructions
-----------------------------------------------------------------------------
constant RET : std_logic_vector(7 downto 0) := X"C3"; -- Within Segment
constant RETDIS : std_logic_vector(7 downto 0) := X"CB"; -- Direct Inter Segment
constant RETO : std_logic_vector(7 downto 0) := X"C2"; -- Within Segment + Offset
constant RETDISO : std_logic_vector(7 downto 0) := X"CA"; -- Direct Inter Segment +Offset
-----------------------------------------------------------------------------
-- INT Instructions
-----------------------------------------------------------------------------
constant INT : std_logic_vector(7 downto 0) := X"CD"; -- type=second byte
constant INT3 : std_logic_vector(7 downto 0) := X"CC"; -- type=3
constant INTO : std_logic_vector(7 downto 0) := X"CE"; -- type=4
constant IRET : std_logic_vector(7 downto 0) := X"CF"; -- Interrupt Return
-----------------------------------------------------------------------------
-- String/Repeat Instructions
-----------------------------------------------------------------------------
constant MOVSB : std_logic_vector(7 downto 0) := X"A4";
constant MOVSW : std_logic_vector(7 downto 0) := X"A5";
constant CMPSB : std_logic_vector(7 downto 0) := X"A6";
constant CMPSW : std_logic_vector(7 downto 0) := X"A7";
constant SCASB : std_logic_vector(7 downto 0) := X"AE";
constant SCASW : std_logic_vector(7 downto 0) := X"AF";
constant LODSB : std_logic_vector(7 downto 0) := X"AC";
constant LODSW : std_logic_vector(7 downto 0) := X"AD";
constant STOSB : std_logic_vector(7 downto 0) := X"AA";
constant STOSW : std_logic_vector(7 downto 0) := X"AB";
constant REPNE : std_logic_vector(7 downto 0) := X"F2"; -- stop if zf=1
constant REPE : std_logic_vector(7 downto 0) := X"F3"; -- stop if zf/=1
-----------------------------------------------------------------------------
-- Shift/Rotate Instructions
-- Operation define in MODRM REG bits
-- Note REG=110 is undefined
-----------------------------------------------------------------------------
constant SHFTROT0 : std_logic_vector(7 downto 0) := X"D0";
constant SHFTROT1 : std_logic_vector(7 downto 0) := X"D1";
constant SHFTROT2 : std_logic_vector(7 downto 0) := X"D2";
constant SHFTROT3 : std_logic_vector(7 downto 0) := X"D3";
-----------------------------------------------------------------------------
-- FF/FE Instructions. Use regfiled to decode operation
-- INC reg=000 (FF/FE)
-- DEC reg=001 (FF/FE)
-- CALL reg=010 (FF) Indirect within segment
-- CALL reg=011 (FF) Indirect Intersegment
-- JMP reg=100 (FF) Indirect within segment
-- JMP reg=101 (FF) Indirect Intersegment
-- PUSH reg=110 (FF)
-----------------------------------------------------------------------------
constant FEINSTR : std_logic_vector(7 downto 0) := X"FE";
constant FFINSTR : std_logic_vector(7 downto 0) := X"FF";
END cpu86instr;
-- VHDL Entity CPU.biufsm.interface
--
-- Created:
-- by - Hans.UNKNOWN (DIONYSUS)
-- at - 17:43:53 07/10/2006
--
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
LIBRARY CPU;
USE CPU.cpu86pack.ALL;
USE CPU.cpu86instr.ALL;
ENTITY biufsm IS
PORT(
clk : IN std_logic;
flush_coming : IN std_logic;
flush_req : IN std_logic;
irq : IN std_logic;
irq_type : IN std_logic_vector (1 DOWNTO 0);
opc_req : IN std_logic;
read_req : IN std_logic;
reg1freed : IN std_logic; -- Delayed version (1 clk) of reg1free
reg4free : IN std_logic;
regnbok : IN std_logic;
reset : IN std_logic;
w_biufsm_s : IN std_logic;
write_req : IN std_logic;
addrplus4 : OUT std_logic;
biu_error : OUT std_logic;
irq_clr : OUT std_logic;
latchabus : OUT std_logic;
latchclr : OUT std_logic;
latchm : OUT std_logic;
latcho : OUT std_logic;
latchrw : OUT std_logic;
ldposplus1 : OUT std_logic;
muxabus : OUT std_logic_vector (1 DOWNTO 0);
rdcode_s : OUT std_logic;
rddata_s : OUT std_logic;
regplus1 : OUT std_logic;
rw_ack : OUT std_logic;
wr_s : OUT std_logic;
flush_ack : BUFFER std_logic;
inta1 : BUFFER std_logic
);
-- Declarations
END biufsm ;
--
-- VHDL Architecture CPU.biufsm.fsm
--
-- Created:
-- by - Hans.UNKNOWN (DIONYSUS)
-- at - 17:43:54 07/10/2006
--
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
LIBRARY CPU;
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