📄 top_struct.vhd
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-------------------------------------------------------------------------------
-- --
-- CPU86 - VHDL CPU8088 IP core --
-- Copyright (C) 2005 HT-LAB --
-- --
-- Contact : mailto:cpu86@ht-lab.com --
-- Web: http://www.ht-lab.com --
-- --
-------------------------------------------------------------------------------
-- --
-- This library is free software; you can redistribute it and/or --
-- modify it under the terms of the GNU Lesser General Public --
-- License as published by the Free Software Foundation; either --
-- version 2.1 of the License, or (at your option) any later version. --
-- --
-- This library is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU --
-- Lesser General Public License for more details. --
-- --
-- Full details of the license can be found in the file "copying.txt". --
-- --
-- You should have received a copy of the GNU Lesser General Public --
-- License along with this library; if not, write to the Free Software --
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA --
-- --
-------------------------------------------------------------------------------
--
-- VHDL Architecture web_example.Top.symbol
--
-- Created: by - Hans 27/08/2005
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
ENTITY Top IS
PORT(
clk : IN std_logic;
cpu_resetn : IN std_logic;
rxd1 : IN std_logic;
rxd2 : IN std_logic;
user_pbx : IN std_logic_vector (3 DOWNTO 0);
fse_a : OUT std_logic_vector (22 DOWNTO 0);
ledg : OUT std_logic_vector (7 DOWNTO 0);
outport : OUT std_logic_vector (7 DOWNTO 0);
sram_be_n : OUT std_logic_vector (3 DOWNTO 0);
sram_cs_n : OUT std_logic;
sram_oe_n : OUT std_logic;
sram_we_n : OUT std_logic;
txd1 : OUT std_logic;
txd2 : OUT std_logic;
fse_d : INOUT std_logic_vector (31 DOWNTO 0)
);
-- Declarations
END Top ;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
LIBRARY CPU;
ARCHITECTURE struct OF Top IS
-- Architecture declarations
signal csromn : std_logic;
signal csembram : std_logic;
-- Internal signal declarations
SIGNAL abus : std_logic_vector(19 DOWNTO 0);
SIGNAL biu_error : std_logic;
SIGNAL csramn : std_logic;
SIGNAL dbus_embram : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL dbus_ext : std_logic_vector(7 DOWNTO 0);
SIGNAL dbus_in_cpu : std_logic_vector(7 DOWNTO 0);
SIGNAL dbus_io : std_logic_vector(7 DOWNTO 0);
SIGNAL dbus_out_cpu : std_logic_vector(7 DOWNTO 0);
SIGNAL dbus_rom : std_logic_vector(7 DOWNTO 0);
SIGNAL inport : std_logic_vector(7 DOWNTO 0);
SIGNAL intr : std_logic;
SIGNAL iom : std_logic;
SIGNAL lock : std_logic;
SIGNAL nmi : std_logic;
SIGNAL por : std_logic;
SIGNAL proc_error : std_logic;
SIGNAL rdn : std_logic;
SIGNAL resetn : std_logic;
SIGNAL sel_s : std_logic_vector(2 DOWNTO 0);
SIGNAL step_mux : std_logic;
SIGNAL step_on : std_logic;
SIGNAL test : std_logic;
SIGNAL tx2 : std_logic;
SIGNAL txmon : std_logic;
SIGNAL wran : std_logic;
SIGNAL wrena : std_logic;
SIGNAL wrn : std_logic;
-- Component Declarations
COMPONENT cpu86
PORT (
clk : IN std_logic ;
dbus_in : IN std_logic_vector (7 DOWNTO 0);
intr : IN std_logic ;
nmi : IN std_logic ;
por : IN std_logic ;
step_sw : IN std_logic ;
test : IN std_logic ;
abus : OUT std_logic_vector (19 DOWNTO 0);
biu_error : OUT std_logic ;
dbus_out : OUT std_logic_vector (7 DOWNTO 0);
inta : OUT std_logic ;
iom : OUT std_logic ;
lock : OUT std_logic ;
proc_error : OUT std_logic ;
rdn : OUT std_logic ;
resoutn : OUT std_logic ;
step_mux : OUT std_logic ;
step_on : OUT std_logic ;
txmon : OUT std_logic ;
wran : OUT std_logic ;
wrn : OUT std_logic
);
END COMPONENT;
COMPONENT superio_top
GENERIC (
COM_DIVIDER : integer := 15;
TMR_DIVIDER91 : integer := 359256;
UART2_G : boolean := TRUE
);
PORT (
abus : IN std_logic_vector (15 DOWNTO 0);
clk : IN std_logic ;
dbusin : IN std_logic_vector (7 DOWNTO 0);
inport : IN std_logic_vector (7 DOWNTO 0);
iom : IN std_logic ;
rdn : IN std_logic ;
resetn : IN std_logic ;
rx1 : IN std_logic ;
rx2 : IN std_logic ;
wrn : IN std_logic ;
dbusout : OUT std_logic_vector (7 DOWNTO 0);
outport : OUT std_logic_vector (7 DOWNTO 0);
pulse182 : OUT std_logic ;
tx1 : OUT std_logic ;
tx2 : OUT std_logic
);
END COMPONENT;
COMPONENT embedded_rom
PORT (
address : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
clock : IN STD_LOGIC;
q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
END COMPONENT;
COMPONENT embedded_sram
PORT (
address : IN STD_LOGIC_VECTOR (13 DOWNTO 0);
clock : IN STD_LOGIC;
data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
wren : IN STD_LOGIC;
q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
END COMPONENT;
-- Optional embedded configurations
FOR ALL : cpu86 USE ENTITY CPU.cpu86;
BEGIN
-- Architecture concurrent statements
-- HDL Embedded Text Block 2 eb2
-- eb1 1
txd2 <= txmon when step_mux='1' else tx2;
-- HDL Embedded Text Block 3 BSP1
-- Board Support Package/Interface
-- BSP 2
-- Reset, need to fix!, mixture of active high and low
por <= not cpu_resetn;
-- Address(23)/Databus(32)
fse_a <= "000" & abus;
process(abus,csramn)
begin
if (csramn='0') then
case abus(1 downto 0) is
when "00" => sram_be_n <= "1110";
when "01" => sram_be_n <= "1101";
when "10" => sram_be_n <= "1011";
when others => sram_be_n <= "0111";
end case;
else
sram_be_n <= "1111";
end if;
end process;
sram_oe_n <= rdn;
sram_we_n <= wran; -- use async wr, this is negated asserted on the falling edge of clk!
sram_cs_n <= csramn;
-- unused signals
-- Leds and switches
-- Leds active high
ledg(0) <= proc_error;
ledg(1) <= biu_error;
ledg(2) <= step_on;
ledg(3) <= step_mux;
ledg(4) <= '0';
ledg(5) <= not lock;
ledg(6) <= not user_pbx(2);
ledg(7) <= not user_pbx(3); -- use to start the load86 monitor
nmi <= not user_pbx(2); -- test only
--intr <= not user_pbx(3); -- test only
inport <= "0000" & user_pbx;
-- HDL Embedded Text Block 4 dmux2
-- dmux 1
--sel_s <= csromn & csembram & iom;
process(sel_s, dbus_rom, dbus_embram, dbus_io,dbus_ext)
begin
case sel_s is
when "010" => dbus_in_cpu <= dbus_rom;
when "100" => dbus_in_cpu <= dbus_embram;
when "111" => dbus_in_cpu <= dbus_io;
when others=> dbus_in_cpu <= dbus_ext;
end case;
end process;
-- HDL Embedded Text Block 7 chip_select2
-- chip_select 4
-- cpu databus in multiplexer signal
sel_s <= csromn & csembram & iom;
-- Bootstrap ROM 256 bytes (32 words)
-- FFFFF-FF=FFF00
csromn <= '0' when ((abus(19 downto 8)=X"FFF") AND iom='0') else '1';
-- 32Kbyte, FFFFF-8000=F8000
--csromn <= '0' when ((abus(19 downto 14)="111111") AND iom='0') else '1';
-- 16Kbyte
csembram <= '0' when ((abus(19 downto 14)="000000") AND iom='0') else '1';
wrena <= '1' when (csembram='0' AND wrn='0') else '0';
-- External Memory 1MByte - Bootstrap ROM - Embedded RAM
csramn <= '0' when (csromn='1' AND csembram='1' AND iom='0') else '1';
-- HDL Embedded Text Block 8 tristate2
-- eb2 2
process (wrn,dbus_out_cpu)
begin
case wrn is
when '0' => fse_d<= dbus_out_cpu & dbus_out_cpu & dbus_out_cpu & dbus_out_cpu; -- drive port
-- when '1' => fse_d<= (others => 'Z') after 10 ns;
when others => fse_d<= (others => 'Z') after 10 ns;
end case;
end process;
process (abus, fse_d)
begin
case abus(1 downto 0) is
when "00" => dbus_ext <= fse_d(7 downto 0);
when "01" => dbus_ext <= fse_d(15 downto 8);
when "10" => dbus_ext <= fse_d(23 downto 16);
when others => dbus_ext <= fse_d(31 downto 24);
end case;
end process;
-- ModuleWare code(v1.5) for instance 'U_4' of 'gnd'
intr <= '0';
-- ModuleWare code(v1.5) for instance 'U_5' of 'gnd'
test <= '0';
-- Instance port mappings.
U_0 : cpu86
PORT MAP (
clk => clk,
dbus_in => dbus_in_cpu,
intr => intr,
nmi => nmi,
por => por,
step_sw => proc_error,
test => test,
abus => abus,
biu_error => biu_error,
dbus_out => dbus_out_cpu,
inta => OPEN,
iom => iom,
lock => lock,
proc_error => proc_error,
rdn => rdn,
resoutn => resetn,
step_mux => step_mux,
step_on => step_on,
txmon => txmon,
wran => wran,
wrn => wrn
);
U_1 : superio_top
GENERIC MAP (
COM_DIVIDER => 52,
TMR_DIVIDER91 => 359256,
UART2_G => TRUE
)
PORT MAP (
abus => abus(15 DOWNTO 0),
clk => clk,
dbusin => dbus_out_cpu,
inport => inport,
iom => iom,
rdn => rdn,
resetn => resetn,
rx1 => rxd1,
rx2 => rxd2,
wrn => wrn,
dbusout => dbus_io,
outport => outport,
pulse182 => OPEN,
tx1 => txd1,
tx2 => tx2
);
U_2 : embedded_rom
PORT MAP (
address => abus(7 DOWNTO 0),
clock => clk,
q => dbus_rom
);
U_3 : embedded_sram
PORT MAP (
address => abus(13 DOWNTO 0),
clock => clk,
data => dbus_out_cpu,
wren => wrena,
q => dbus_embram
);
END struct;
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