📄 top_tb_struct.vhd
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-------------------------------------------------------------------------------
-- --
-- CPU86 - VHDL CPU8088 IP core --
-- Copyright (C) 2005 HT-LAB --
-- --
-- Contact : mailto:cpu86@ht-lab.com --
-- Web: http://www.ht-lab.com --
-- -- --
-------------------------------------------------------------------------------
-- --
-- This library is free software; you can redistribute it and/or --
-- modify it under the terms of the GNU Lesser General Public --
-- License as published by the Free Software Foundation; either --
-- version 2.1 of the License, or (at your option) any later version. --
-- --
-- This library is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU --
-- Lesser General Public License for more details. --
-- --
-- Full details of the license can be found in the file "copying.txt". --
-- --
-- You should have received a copy of the GNU Lesser General Public --
-- License along with this library; if not, write to the Free Software --
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA --
-- --
-------------------------------------------------------------------------------
--
-- VHDL Architecture web_example.Top_tb.symbol
--
-- Created: by - Hans 27/08/2005
-------------------------------------------------------------------------------
ENTITY Top_tb IS
-- Declarations
END Top_tb ;
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE ieee.std_logic_unsigned.all;
LIBRARY std;
USE std.textio.all;
USE work.utils.all;
ARCHITECTURE struct OF Top_tb IS
-- Architecture declarations
signal dind1_s : std_logic;
signal dind2_s : std_logic;
-- Internal signal declarations
SIGNAL be_n : std_logic_vector(3 DOWNTO 0);
SIGNAL clk_s : std_logic := '0';
SIGNAL cpu_resetn : std_logic;
SIGNAL fse_a : std_logic_vector(22 DOWNTO 0);
SIGNAL fse_d : std_logic_vector(31 DOWNTO 0);
SIGNAL rdn_s : std_logic; -- Active Low Read Pulse (CLK)
SIGNAL rdrf : std_logic;
SIGNAL resoutn : std_logic;
SIGNAL rxenable : std_logic;
SIGNAL rxtb : std_logic;
SIGNAL sram_cs_n : std_logic;
SIGNAL sram_oe_n : std_logic;
SIGNAL sram_we_n : std_logic;
SIGNAL txcmd : std_logic;
SIGNAL txd1 : std_logic;
SIGNAL txd2 : std_logic;
SIGNAL txenable : std_logic;
SIGNAL udbus : Std_Logic_Vector(7 DOWNTO 0);
SIGNAL user_pbx : std_logic_vector(3 DOWNTO 0);
-- Component Declarations
COMPONENT uartrx
PORT (
clk : IN std_logic ;
enable : IN std_logic ; -- 16 x bit_rate receive clock enable
resetn : IN std_logic ;
dbus : OUT std_logic_vector (7 DOWNTO 0);
rdn : IN std_logic ;
rdrf : OUT std_logic ;
ferror : OUT std_logic ;
rx : IN std_logic
);
END COMPONENT;
COMPONENT Top
PORT (
clk : IN std_logic ;
cpu_resetn : IN std_logic ;
rxd1 : IN std_logic ;
rxd2 : IN std_logic ;
user_pbx : IN std_logic_vector (3 DOWNTO 0);
fse_a : OUT std_logic_vector (22 DOWNTO 0);
ledg : OUT std_logic_vector (7 DOWNTO 0);
outport : OUT std_logic_vector (7 DOWNTO 0);
sram_be_n : OUT std_logic_vector (3 DOWNTO 0);
sram_cs_n : OUT std_logic ;
sram_oe_n : OUT std_logic ;
sram_we_n : OUT std_logic ;
txd1 : OUT std_logic ;
txd2 : OUT std_logic ;
fse_d : INOUT std_logic_vector (31 DOWNTO 0)
);
END COMPONENT;
COMPONENT sram32kx16
GENERIC (
tacc : time; -- Access Time
thold : time
);
PORT (
addr : IN std_logic_vector (17 DOWNTO 0);
bhe : IN std_logic;
ble : IN std_logic;
cs : IN std_logic;
oe : IN std_logic;
we : IN std_logic;
data : INOUT std_logic_vector (15 DOWNTO 0)
);
END COMPONENT;
COMPONENT tester
PORT (
cpu_resetn : OUT std_logic ;
rxenable : OUT std_logic ;
txcmd : OUT std_logic ;
user_pbx : OUT std_logic_vector (3 DOWNTO 0);
clk_s : BUFFER std_logic ;
resoutn : BUFFER std_logic ;
txenable : BUFFER std_logic
);
END COMPONENT;
BEGIN
-- Architecture concurrent statements
-- HDL Embedded Text Block 2 eb2
-- eb1 1
rxtb<=txd1 when user_pbx(0)='0' else txd2;
-- HDL Embedded Text Block 3 eb3
-- eb1 1
-- UART Monitor
-- Display string after 80 characters or CR character is received
process (rdrf,resoutn) -- UART Bus Monitor, display 0 terminated string (or char count>39)
variable L : line;
variable i_v : integer;
begin
if resoutn='0' then
i_v := 0; -- clear character counter
elsif (rising_edge(rdrf)) then -- possible, pulse is wide!
if i_v=0 then
write(L,string'("RD UART : "));
if (udbus/=X"0D" and udbus/=X"0A") then
write(L,std_to_char(udbus));
end if;
i_v := i_v+1;
-- elsif (i_v=80 or udbus=X"0A") then
elsif (i_v=80 or udbus=X"0D") then
writeline(output,L);
i_v:=0;
else
if (udbus/=X"0D" and udbus/=X"0A") then
write(L,std_to_char(udbus));
end if;
i_v := i_v+1;
end if;
end if;
end process;
process (clk_s,resoutn) -- First/Second delay
begin
if (resoutn='0') then
dind1_s <= '0';
dind2_s <= '0';
elsif (rising_edge(clk_s)) then
dind1_s <= rdrf;
dind2_s <= dind1_s;
end if;
end process;
rdn_s <= '0' when (dind1_s='1' and dind2_s='0') else '1';
-- Instance port mappings.
U_2 : uartrx
PORT MAP (
clk => clk_s,
enable => rxenable,
resetn => resoutn,
dbus => udbus,
rdn => rdn_s,
rdrf => rdrf,
ferror => OPEN,
rx => rxtb
);
U_0 : Top
PORT MAP (
clk => clk_s,
cpu_resetn => cpu_resetn,
rxd1 => txcmd,
rxd2 => txcmd,
user_pbx => user_pbx,
fse_a => fse_a,
ledg => OPEN,
outport => OPEN,
sram_be_n => be_n,
sram_cs_n => sram_cs_n,
sram_oe_n => sram_oe_n,
sram_we_n => sram_we_n,
txd1 => txd2,
txd2 => txd1,
fse_d => fse_d
);
U_3 : sram32kx16
GENERIC MAP (
tacc => 15 ns, -- Access Time
thold => 5 ns
)
PORT MAP (
addr => fse_a(17 DOWNTO 0),
data => fse_d(15 DOWNTO 0),
we => sram_we_n,
oe => sram_oe_n,
cs => sram_cs_n,
ble => be_n(0),
bhe => be_n(1)
);
U_4 : sram32kx16
GENERIC MAP (
tacc => 15 ns, -- Access Time
thold => 5 ns
)
PORT MAP (
addr => fse_a(17 DOWNTO 0),
data => fse_d(31 DOWNTO 16),
we => sram_we_n,
oe => sram_oe_n,
cs => sram_cs_n,
ble => be_n(2),
bhe => be_n(3)
);
U_1 : tester
PORT MAP (
cpu_resetn => cpu_resetn,
rxenable => rxenable,
txcmd => txcmd,
user_pbx => user_pbx,
clk_s => clk_s,
resoutn => resoutn,
txenable => txenable
);
END struct;
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