sram.v

来自「这个是用可编程器件进行仿真CPU的程序」· Verilog 代码 · 共 102 行

//**************************************************
//** Revision    :  0.1
//** File name   :  SRAM.v
//** Module name :  SRAM
//** Discription :  Discripte a 8-bit X16 RAM
//** Simulator   :  Quartus II V5.1 web edition
//** Synthesizer :  Quartus II V5.1 web edition
//** Author      :  IamFree
//** Last modified:    @ 2006///
//** Created date:  2006/03/23
//**************************************************

module SRAM(datao,datai,address,nWR,nCS,CLK);
//Parameter define
parameter width=8;

//Port define
output [width-1:0] datao;
input [width-1:0] datai;
input [3:0] address;    //Address bus
input nWR;              //RAM write signal,active low.
input nCS;              //RAM select signal,active low.
input CLK;

reg [width-1:0] datao;

//Register stack,as Quartus don't support register array
reg [width-1:0] byte0;
reg [width-1:0] byte1;
reg [width-1:0] byte2;
reg [width-1:0] byte3;
reg [width-1:0] byte4;

reg [width-1:0] byte5;
reg [width-1:0] byte6;
reg [width-1:0] byte7;
reg [width-1:0] byte8;
reg [width-1:0] byte9;
reg [width-1:0] byte10;
reg [width-1:0] byte11;
reg [width-1:0] byte12;
reg [width-1:0] byte13;
reg [width-1:0] byte14;
reg [width-1:0] byte15;

//Body
always @(posedge CLK)
if(!nCS & !nWR)
    case(address)  //synthesis parallel_case
     4'b0000:byte0<=datai;
     4'b0001:byte1<=datai;
     4'b0010:byte2<=datai;
     4'b0011:byte3<=datai;

     4'b0100:byte4<=datai;
     4'b0101:byte5<=datai;
     4'b0110:byte6<=datai;
     4'b0111:byte7<=datai;

     4'b1000:byte8<=datai;
     4'b1001:byte9<=datai;
     4'b1010:byte10<=datai;
     4'b1011:byte11<=datai;

     4'b1100:byte12<=datai;
     4'b1101:byte13<=datai;
     4'b1110:byte14<=datai;
     4'b1111:byte15<=datai;
    endcase

 always @(address or byte0 or byte1 or byte2 or byte3 or
          byte4 or byte5 or byte6 or byte7 or
          byte8 or byte9 or byte10 or byte11 or
          byte12 or byte13 or byte14 or byte15
         )//读寄存器
  begin
   case(address)  //synthesis parallel_case
     4'b0000:datao=byte0;
     4'b0001:datao=byte1;
     4'b0010:datao=byte2;
     4'b0011:datao=byte3;

     4'b0100:datao=byte4;
     4'b0101:datao=byte5;
     4'b0110:datao=byte6;
     4'b0111:datao=byte7;

     4'b1000:datao=byte8;
     4'b1001:datao=byte9;
     4'b1010:datao=byte10;
     4'b1011:datao=byte11;

     4'b1100:datao=byte12;
     4'b1101:datao=byte13;
     4'b1110:datao=byte14;
     4'b1111:datao=byte15;    
   endcase
  end

endmodule