ram.v

这个是用可编程器件进行仿真CPU的程序

//**************************************************
//** Revision    :  0.1
//** File name   :  RAM.v
//** Module name :  ram
//** Discription :  Discripte a 8-bit X16 RAM
//** Simulator   :  Quartus II V5.1 web edition
//** Synthesizer :  Quartus II V5.1 web edition
//** Author      :  IamFree
//** Last modified:    @ 2006///
//** Created date:  2006/03/23
//**************************************************

module RAM(data,address,nRD,nWR,nCS);
//Parameter define
parameter width=8;

//Port define
inout [width-1:0] data; //Bidir data bus
input [3:0] address;    //Address bus
input nRD;              //RAM read signal,active low.
input nWR;              //RAM write signal,active low.
input nCS;              //RAM select signal,active low.

//Register stack,as Quartus don't support register array
reg [width-1:0] byte0;
reg [width-1:0] byte1;
reg [width-1:0] byte2;
reg [width-1:0] byte3;
reg [width-1:0] byte4;

reg [width-1:0] byte5;
reg [width-1:0] byte6;
reg [width-1:0] byte7;
reg [width-1:0] byte8;
reg [width-1:0] byte9;
reg [width-1:0] byte10;
reg [width-1:0] byte11;
reg [width-1:0] byte12;
reg [width-1:0] byte13;
reg [width-1:0] byte14;
reg [width-1:0] byte15;

//Veriabel define
reg [width-1:0] temp;

//Body
assign data=nCS?8'bZZZZ_ZZZZ:(nWR?(nRD?8'bZZZZ_ZZZZ:temp):8'bZZZZ_ZZZZ);

always @(nRD or nWR)
if(!nCS)
 begin
  if(!nWR)
    case(address)  //synthesis parallel_case
     4'b0000:byte0=data;
     4'b0001:byte1=data;
     4'b0010:byte2=data;
     4'b0011:byte3=data;

     4'b0100:byte4=data;
     4'b0101:byte5=data;
     4'b0110:byte6=data;
     4'b0111:byte7=data;

     4'b1000:byte8=data;
     4'b1001:byte9=data;
     4'b1010:byte10=data;
     4'b1011:byte11=data;

     4'b1100:byte12=data;
     4'b1101:byte13=data;
     4'b1110:byte14=data;
     4'b1111:byte15=data;
    endcase
   else if(!nRD)
    case(address) //synthesis parallel_case
     4'b0000:temp=byte0;
     4'b0001:temp=byte1;
     4'b0010:temp=byte2;
     4'b0011:temp=byte3;

     4'b0100:temp=byte4;
     4'b0101:temp=byte5;
     4'b0110:temp=byte6;
     4'b0111:temp=byte7;

     4'b1000:temp=byte8;
     4'b1001:temp=byte9;
     4'b1010:temp=byte10;
     4'b1011:temp=byte11;

     4'b1100:temp=byte12;
     4'b1101:temp=byte13;
     4'b1110:temp=byte14;
     4'b1111:temp=byte15;
    endcase
 end

endmodule