gr6.v

这个是用可编程器件进行仿真CPU的程序

//**************************************************
//** Revision    :  0.1
//** File name   :  GR6.v
//** Module name :  GR6
//** Discription :  A 6 X 8-bit addressed register
//** Simulator   :  Max+plus II
//** Synthesizer :  Max+plus II
//** Author      :  IamFree
//** Last modify :    @ 2006///
//** Create date :  2006/03/08
//**************************************************

module GR6(Dout,ACC_sel,PSW_sel,Din,clk,ld,GR6_address);
//Parameter define
parameter width =8;

//Port define
output [width-1:0] Dout;
output ACC_sel;
output PSW_sel;
input  [width-1:0] Din;
input  clk;
input  ld;
input  [2:0] GR6_address;

integer i;
//Port type
reg    [width-1:0] Dout;
reg    [width-1:0] register1;
reg    [width-1:0] register2;
reg    [width-1:0] register3;
reg    [width-1:0] register4;
reg    [width-1:0] register5;
reg    [width-1:0] register6;

//Body
always @(posedge clk)
 begin
  if(ld) //写寄存器
   begin
    case(GR6_address)
     3'b001:register1<=Din;
     3'b010:register2<=Din;
     3'b011:register3<=Din;
     3'b100:register4<=Din;
     3'b101:register5<=Din;
     3'b110:register6<=Din;
     endcase
   end
 end

 always @(GR6_address or register1 or register2 or register3
           or register4 or register5 or register6)//读寄存器
  begin
   case(GR6_address)
    3'b000:Dout=8'bXXXX_XXXX;
    3'b001:Dout=register1;
    3'b010:Dout=register2;
    3'b011:Dout=register3;
    3'b100:Dout=register4;
    3'b101:Dout=register5;
    3'b110:Dout=register6;
    3'b111:Dout=8'b0000_0000;
   endcase
  end


assign ACC_sel=(GR6_address==3'b000)?1'b1:1'b0;
assign PSW_sel=(GR6_address==3'b111)?1'b1:1'b0;

endmodule