tongxin.v

这个是用可编程器件进行仿真CPU的程序

//**************************************************
//** Revision    :  0.1
//** File name   :  TongXin.v
//** Module name :  TongXin
//** Discription :  The top-level module of the Taocore CPU
//** Simulator   :  Quartus II 5.1 web edition full
//** Synthesizer :  Quartus II 5.1 web edition full
//** Author      :  IamFree
//** Last modified:    @ 2006///
//** Created date:  2006/03/24
//**************************************************

module TongXin(
   ADDRESS,  //Taocore's address bus
   DATA,     //Taocore's data bus.It is Input/Output time sperated
   nWR,      //Memory write enable signal ("n" means this signal is active low,the same below)
   nRD,      //Memory read enable signal
   nROM_CS,  //Code memory chip select
   nRAM_CS,  //Data memory chip select
   nRESET,   //System reset signal
   CLOCK,    //System clock signal
   PORT      //General purpose IO port
);


//Parameter define
parameter width=8;
parameter address_width=11;
parameter ZZZ=8'bZZZZ_ZZZZ;
parameter LOW=8'b0000_0000;

//Port define
output [address_width-1:0] ADDRESS;
output nWR;
output nRD;
output nROM_CS;
output nRAM_CS;

input  nRESET;
input  CLOCK;

inout  [width-1:0] DATA;
//Extra port
inout  [width-1:0] PORT;

//Internal wire define
wire [4:0] d2c_opcode;   //"d2c" means Signal(s) from datapath to CU
wire [2:0] d2c_flags;
wire [1:0] d2c_sel_flags;

wire [4:0] c2d_alu_func; //"c2d" means Signal(s) from CU to datapath

wire c2d_LD_acc;
wire c2d_LD_arl;
wire c2d_LD_pcl;
wire c2d_LD_ir;
wire c2d_LD_spl;
wire c2d_LD_sph;
wire c2d_LD_arh;
wire c2d_LD_pch;
wire c2d_LD_psw;
wire c2d_LD_gr6;


wire c2d_SEL_arh;
wire c2d_SEL_gr_addr;
wire c2d_SEL_psw;
wire [1:0] c2d_SEL_alu;
wire [1:0] c2d_SEL_sp;
wire [1:0] c2d_SEL_databus;
wire c2d_SEL_pc;
wire [1:0] c2d_SEL_address;
wire c2d_data_out_enable;

wire [width-1:0] d2_data_out;
wire [width-1:0] d2_data_in;

//Body

CU mcu(
//inputs
.opcode(d2c_opcode),
.flags(d2c_flags),
.sel_flags(d2c_sel_flags),
.sys_clk(CLOCK),
.sys_rst(nRESET),

//outputs
.alu_func(c2d_alu_func),

.LD_acc(c2d_LD_acc),
.LD_arl(c2d_LD_arl),
.LD_pcl(c2d_LD_pcl),
.LD_ir (c2d_LD_ir),
.LD_spl(c2d_LD_spl),
.LD_sph(c2d_LD_sph),
.LD_arh(c2d_LD_arh),
.LD_pch(c2d_LD_pch),
.LD_psw(c2d_LD_psw),
.LD_gr6(c2d_LD_gr6),


.SEL_arh(c2d_SEL_arh),
.SEL_gr_addr(c2d_SEL_gr_addr),
.SEL_psw(c2d_SEL_psw),
.SEL_alu(c2d_SEL_alu),
.SEL_sp(c2d_SEL_sp),
.SEL_databus(c2d_SEL_databus),
.SEL_pc(c2d_SEL_pc),
.SEL_address(c2d_SEL_address),

//data bus control
.rom_cs(nROM_CS),
.ram_cs(nRAM_CS),
.mem_wr(nWR),
.mem_rd(nRD),
.data_out_enable(c2d_data_out_enable)
);

datapath mdatapath(
//outputs
.address(ADDRESS),         //Memory address
.opcode(d2c_opcode),       //Opcode that send to CU
.flags(d2c_flags),         //Flags in PSW
.sel_flags(d2c_sel_flags), //ACC,PSW addressing signal
//inputs
.sys_clk(CLOCK),           //System clock
.sys_rst(nRESET),          //System reset
.alu_func(c2d_alu_func),   //ALU function select

.LD_acc(c2d_LD_acc),       //All the port names that start with "LD_"
.LD_arl(c2d_LD_arl),       //are registers' load enable signals.
.LD_pcl(c2d_LD_pcl),
.LD_ir (c2d_LD_ir),
.LD_spl(c2d_LD_spl),
.LD_sph(c2d_LD_sph),
.LD_arh(c2d_LD_arh),
.LD_pch(c2d_LD_pch),
.LD_psw(c2d_LD_psw),
.LD_gr6(c2d_LD_gr6),

.SEL_arh(c2d_SEL_arh),         //All the port names that start with "SEL_"
.SEL_gr_addr(c2d_SEL_gr_addr), //are MUXs' selection signals.
.SEL_psw(c2d_SEL_psw),
.SEL_alu(c2d_SEL_alu),
.SEL_sp(c2d_SEL_sp),
.SEL_databus(c2d_SEL_databus),
.SEL_pc(c2d_SEL_pc),
.SEL_address(c2d_SEL_address),

//inout
.data_in(d2_data_in),
.data_out(d2_data_out)
);

//Memory modules
wire sel_ram;
wire sel_io;
wire [width-1:0] rom_data;
wire [width-1:0] ram_data;
wire [width-1:0] idata;

//Data bus control
assign sel_ram=ADDRESS[10]|nRAM_CS;   //RAM: 000-3ff
assign sel_io=(!ADDRESS[10])|nRAM_CS; //IO : 400-7ff 

assign idata=c2d_data_out_enable?d2_data_out:DATA;

assign d2_data_in=nROM_CS?((nRAM_CS | nRD)?idata:ram_data):rom_data;

assign DATA=c2d_data_out_enable?d2_data_out:ZZZ;

IO mio(.port(PORT),
       .datao(ram_data),
       .datai(d2_data_out),
       .addr(ADDRESS[1:0]),
       .nCS(sel_io),
       .nRD(nRD),
       .nWR(nWR),
       .CLK(CLOCK),
       .nRST(nRESET)
);

SRAM mram(.datao(ram_data),
         .datai(d2_data_out),
         .address(ADDRESS[3:0]),
         .nWR(nWR),
         .nCS(sel_ram),
         .CLK(CLOCK)
);

rom mrom(.dout(rom_data),
         .nRD(nRD),
         .nCS(nROM_CS),
         .address(ADDRESS[3:0])
);

endmodule