add_one11.v

来自「这个是用可编程器件进行仿真CPU的程序」· Verilog 代码 · 共 31 行

//**************************************************
//** Revision    :  0.1
//** File name   :  add_one11.v
//** Module name :  add_one11
//** Discription :  A 11-bit integer added with 1
//** Simulator   :  Max+plus II
//** Synthesizer :  Max+plus II
//** Author      :  IamFree
//** Last modified:    @ 2006///
//** Created date:  2006/03/08
//**************************************************

module add_one11(a1_O,a1_I);

//Parameter define
parameter width=11;

//Port define
output [width-1:0] a1_O;
input  [width-1:0] a1_I;

//Port type
reg    [width-1:0] a1_O;

//Body
always @(a1_I)
  a1_O=a1_I+11'b0000_0000_001;

endmodule