io.v

这个是用可编程器件进行仿真CPU的程序

//**************************************************
//** Revision    :  0.1
//** File name   :  IO.v
//** Module name :  IO
//** Discription :  A general IO port
//** Simulator   :  Quartus II 5.1 web edition full
//** Synthesizer :  Quartus II 5.1 web edition full
//** Author      :  IamFree
//** Last modified:    @ 2006///
//** Created date:  2006/03/24
//**************************************************
/*
addr      function
00    Read or write the IO port's buffer
01    Read the IO port,write is invalid
10    Read or write the direction ctrl word
11    Reserved
*/

module IO(port,datao,datai,addr,nCS,nRD,nWR,CLK,nRST);
//Parameter define
parameter width=8;

parameter INPUT=8'b0000_0000;
parameter LOW=8'b0000_0000;
parameter ZZZ=8'bZZZZ_ZZZZ;

parameter IO_TEMP=2'b00;  //IO module internal addressing
parameter IO_PORT=2'b01;
parameter IO_DIR =2'b10;
parameter IO_RSV =2'b11;

//Port define
inout [width-1:0] port;
inout [width-1:0] datao;
input [width-1:0] datai;
input [1:0] addr;       //Address
input nCS;    //Module enable,active low
input nRD;    //Read enable,active low
input nWR;    //Write enable,active low
input CLK;    //Clock
input nRST;   //Reset

//Port type

//Veriable define
reg [width-1:0] temp_data;
reg [width-1:0] dir;

//Body

//Port direction control
assign port[0]=dir[0]?temp_data[0]:1'bZ; 
assign port[1]=dir[1]?temp_data[1]:1'bZ;
assign port[2]=dir[2]?temp_data[2]:1'bZ;
assign port[3]=dir[3]?temp_data[3]:1'bZ;
assign port[4]=dir[4]?temp_data[4]:1'bZ;
assign port[5]=dir[5]?temp_data[5]:1'bZ;
assign port[6]=dir[6]?temp_data[6]:1'bZ;
assign port[7]=dir[7]?temp_data[7]:1'bZ;

//Data bus control
assign datao=nCS?ZZZ:
                 (nRD?ZZZ:( (addr==IO_TEMP)?temp_data:
                          ( (addr==IO_PORT)?port:
                           ((addr==IO_DIR)? dir:
                            LOW)
                           )
                          )
                 );

//Registers control
always @(posedge CLK or negedge nRST)
if(!nRST)
 begin
  dir<=INPUT; //Default direction is input
  temp_data<=LOW;
 end
else
 if(!nCS && !nWR)
   case(addr) //synthesis parallel_case
    IO_TEMP: temp_data<=datai;
    IO_PORT:;
    IO_DIR: dir<=datai;
    IO_RSV: ;
   endcase

endmodule