cu.v

这个是用可编程器件进行仿真CPU的程序

          rom_cs=ENABLE;   //MEM type
          mem_rd=ENABLE;
          SEL_alu=SEL_ALU_MEM;
          alu_func=ALU_TB;
          SEL_databus=SEL_DATABUS_ALU;
          LD_arl=LDEN;

          SC_inc=1'b1;
         end
        S2 :
         begin
          LD_acc=LDDIS;
          //PC<-AR
          SEL_pc=SEL_PC_AR;
          LD_pch=LDEN;LD_pcl=LDEN;
          SC_clr_n=1'b0;
         end
        default:SC_clr_n=1'b0;
       endcase
     end
     else
      SC_clr_n=1'b0; //OR fetch the opcode at the next address
    end

   LDV ,  //STV,LDV,Debugged!
   STV :
    begin
     case(Op_state)//synthesis parallel_case
      S1 :
       begin
        SEL_arh=SEL_ARH_RRR; //ARH<-RRR
        LD_arh=LDEN;
        SC_inc=1'b1;
       end
      S2 :
       begin
        //PC<-PC+1
        SEL_pc=SEL_PC_A1;
        LD_pch=LDEN;LD_pcl=LDEN;

        //ARL<-MEM(code)
        SEL_address=SEL_ADDRESS_PC;
        mem_rd=ENABLE;   //MEM type
        rom_cs=ENABLE;

        SEL_alu=SEL_ALU_MEM; 
        alu_func=ALU_TB; 
        SEL_databus=SEL_DATABUS_ALU;
        LD_arl=LDEN;     //Where is the result going
        SC_inc=1'b1;
       end
      S3 :
       begin
        SEL_address=SEL_ADDRESS_AR;
        SC_inc=1'b1;
       end
      S4 :
       begin
        //address<-AR
        SEL_address=SEL_ADDRESS_AR;
        ram_cs=ENABLE;   //MEM type
        if(opcode==LDV)
         begin    //ACC<-MEM(data)
          mem_rd=ENABLE;
          SEL_alu=SEL_ALU_MEM;
          alu_func=ALU_TB;
          SEL_databus=SEL_DATABUS_ALU;
          LD_acc=LDEN;
         end
        else      //MEM(data)<-ACC
         begin
          mem_wr=ENABLE;
          alu_func=ALU_TA;
          SEL_databus=SEL_DATABUS_ALU;
          data_out_enable=OUTEN;
         end
        SC_clr_n=1'b0;
       end
      default:SC_clr_n=1'b0;
     endcase
    end

   STR ,
   STSPL ,   //STR,STSPH,STSPL debugged
   STSPH :
     begin
        //reg[rrr] or spl or sph<-ACC
        alu_func=ALU_TA;   //What should the alu do
        SEL_databus=SEL_DATABUS_ALU;
        case(opcode[1:0])//synthesis parallel_case
         2'b00: //STR
          begin
           LD_gr6=LDEN;
           SEL_gr_addr=SEL_GR_ADDR_RRR;
          end
         2'b01: //STSPH
          begin
           LD_sph=LDEN;
           SEL_sp=SEL_SP_DATA;
          end
         2'b10: //STSPL
          begin
           LD_spl=LDEN;
           SEL_sp=SEL_SP_DATA;
          end
         default:SC_clr_n=1'b0;
        endcase
      SC_clr_n=1'b0;
    end

   LDI :   //ALL Debugged
    begin
     case(Op_state)//synthesis parallel_case
      S1 :
       begin
        //reg[rrr]<-MEM(code) NOTE: rrr can't be PSW
        SEL_address=SEL_ADDRESS_PC;   //??? May be useless
        mem_rd=ENABLE;  //MEM type
        rom_cs=ENABLE;

        SEL_alu=SEL_ALU_MEM;
        alu_func=ALU_TB;
        SEL_databus=SEL_DATABUS_ALU;

        if(sel_flags[flag_acc_sel]) //Deal with ACC
          LD_acc=LDEN;
        else
         begin
          SEL_gr_addr=SEL_GR_ADDR_RRR;
          LD_gr6=LDEN;
         end
        SC_inc=1'b1;
       end
      S2 :
       begin
        //PC<-PC+1
        SEL_pc=SEL_PC_A1;
        LD_pch=LDEN;LD_pcl=LDEN;
        SC_clr_n=1'b0;
       end
      default:SC_clr_n=1'b0;
     endcase
    end

   LDA ,  //Debugging...(LDA, Debugged)
   STA :
     begin
     case(Op_state)//synthesis parallel_case
      S1 :
       begin
        //ARL<-[BX]
        SEL_gr_addr=SEL_GR_ADDR_BX;
        SEL_alu=SEL_ALU_GR6;
        alu_func=ALU_TB;
        SEL_databus=SEL_DATABUS_ALU;
        LD_arl=LDEN;

        SEL_arh=SEL_ARH_RRR; //ARH<-RRR
        LD_arh=LDEN;
        SC_inc=1'b1;
       end
      S2 :
       begin    
        SEL_address=SEL_ADDRESS_AR;
        SC_inc=1'b1;
       end
      S3 :
       begin
        //MEM type
        ram_cs=ENABLE;

        SEL_address=SEL_ADDRESS_AR; //address<-AR
        if(opcode==LDA)
         begin
          mem_rd=ENABLE;
          SEL_alu=SEL_ALU_MEM;      //ACC<-MEM(data)
          alu_func=ALU_TB;
          SEL_databus=SEL_DATABUS_ALU;
          LD_acc=LDEN;
         end
        else
         begin
          //MEM(data)<-ACC
          mem_wr=ENABLE;
          alu_func=ALU_TA;
          SEL_databus=SEL_DATABUS_ALU;
          data_out_enable=OUTEN;
         end
        SC_clr_n=1'b0;
       end
      default:SC_clr_n=1'b0;
     endcase
    end

   LDR :  //Debuged!
    begin
     //ACC<-reg[rrr] NOTE: rrr can't be ACC or PSW
     SEL_gr_addr=SEL_GR_ADDR_RRR;
     SEL_alu=SEL_ALU_GR6;
     alu_func=ALU_TB;
     SEL_databus=SEL_DATABUS_ALU;
     LD_acc=LDEN;
     SC_clr_n=1'b0;
    end

   CALL :  //Debugged!
    begin
     case(Op_state)//synthesis parallel_case
      S1 :
       begin
        SEL_arh=SEL_ARH_RRR; //ARH<-RRR
        LD_arh=LDEN;
        SC_inc=1'b1;
       end
      S2 :
       begin
        //ARL<-MEM(code)
        SEL_address=SEL_ADDRESS_PC; //ADDRESS<-PC
        mem_rd=ENABLE;  //MEM type
        rom_cs=ENABLE;

        SEL_alu=SEL_ALU_MEM;
        alu_func=ALU_TB;
        SEL_databus=SEL_DATABUS_ALU;
        LD_arl=LDEN;
        SC_inc=1'b1;
       end
      S3 :
       begin
        SEL_address=SEL_ADDRESS_SP;  //address<-SP
        SEL_databus=SEL_DATABUS_PCH; //MEM(data)<-PCH

        mem_wr=ENABLE;
        ram_cs=ENABLE;

        data_out_enable=OUTEN;
        SC_inc=1'b1;
       end
      S4 :
       begin
        SEL_sp=SEL_SP_S1; //SP<-SP-1
        LD_sph=LDEN;LD_spl=LDEN;
        SC_inc=1'b1;
       end
      S5 :
       begin
        SEL_address=SEL_ADDRESS_SP;  //address<-SP????      
        SEL_databus=SEL_DATABUS_PCL;   //MEM(data)<-PCL
        //MEM type
        mem_wr=ENABLE;
        ram_cs=ENABLE;

        data_out_enable=OUTEN;
        SC_inc=1'b1;
       end
      S6 :
       begin
        SEL_sp=SEL_SP_S1; //SP<-SP-1
        LD_spl=LDEN;LD_sph=LDEN;
        SEL_pc=SEL_PC_AR; //PC<-AR
        LD_pcl=LDEN; LD_pch=LDEN;
        SC_clr_n=1'b0;
       end
      default:SC_clr_n=1'b0;
     endcase
    end

   RET :  //Debugged!
     begin
     case(Op_state)//synthesis parallel_case
      S1 :
       begin
        SEL_sp=SEL_SP_A1; //SP<-SP+1
        LD_spl=LDEN;LD_sph=LDEN;
        SC_inc=1'b1;
       end
      S2 :
       begin
        SEL_address=SEL_ADDRESS_SP; //address<-SP
        //ARL<-MEM(data)
        mem_rd=ENABLE;  //MEM type
        ram_cs=ENABLE;
        SEL_alu=SEL_ALU_MEM;
        alu_func=ALU_TB;
        SEL_databus=SEL_DATABUS_ALU;
        LD_arl=LDEN;
        SC_inc=1'b1;
       end
      S3 :
       begin
        SEL_sp=SEL_SP_A1; //SP<-SP+1
        LD_spl=LDEN;LD_sph=LDEN;
        SC_inc=1'b1;
       end
      S4 :
       begin
        SEL_address=SEL_ADDRESS_SP; //address<-SP
        //ARL<-MEM(data)
        mem_rd=ENABLE;  //MEM type
        ram_cs=ENABLE;

        SEL_alu=SEL_ALU_MEM;
        alu_func=ALU_TB;
        SEL_databus=SEL_DATABUS_ALU;
        SEL_arh=SEL_ARH_DATA;  //ARH<-MEM(data)
        LD_arh=LDEN;
        SC_inc=1'b1;
       end
      S5 :
       begin
        SEL_pc=SEL_PC_AR;  //PC<-AR
        LD_pcl=LDEN; LD_pch=LDEN;
        SC_inc=1'b1;
       end
      S6 :
       begin
        SEL_pc=SEL_PC_A1;
        LD_pcl=LDEN; LD_pch=LDEN;
        SC_clr_n=1'b0;
       end
      default:SC_clr_n=1'b0;
     endcase
    end

   PUSH :  //Debugged!
    begin
     case(Op_state)//synthesis parallel_case
      S1 :
       begin
        //address<-SP
        SEL_address=SEL_ADDRESS_SP;
        //MEM(data)<-reg[rrr]
        mem_wr=ENABLE;
        ram_cs=ENABLE;
        if(sel_flags[flag_acc_sel]) //Deal with ACC and PSW
          alu_func=ALU_TA;
        else if(sel_flags[flag_psw_sel])
         begin
          SEL_alu=SEL_ALU_FLAGS;
          alu_func=ALU_TB;
         end
        else
         begin
          SEL_gr_addr=SEL_GR_ADDR_RRR;
          SEL_alu=SEL_ALU_GR6;
          alu_func=ALU_TB;
         end
        SEL_databus=SEL_DATABUS_ALU;
        data_out_enable=OUTEN;
        SC_inc=1'b1;
       end
      S2 :
       begin
        SEL_sp=SEL_SP_S1; //SP<-SP-1
        LD_spl=LDEN;LD_sph=LDEN;
        SC_clr_n=1'b0;
       end
      default:SC_clr_n=1'b0;
     endcase
    end

   POP :  //Debugged!
     begin
     case(Op_state)//synthesis parallel_case
      S1 :
       begin
        //SP<-SP+1
        SEL_sp=SEL_SP_A1;
        LD_spl=LDEN;LD_sph=LDEN;
        SC_inc=1'b1;
       end
      S2 :
       begin
        SEL_address=SEL_ADDRESS_SP; //address<-SP
        //reg[rrr]<-MEM(data)
        mem_rd=ENABLE;  //MEM type
        ram_cs=ENABLE;
        SEL_alu=SEL_ALU_MEM;
        alu_func=ALU_TB;
        SEL_databus=SEL_DATABUS_ALU;
        if(sel_flags[flag_acc_sel]) //Deal with ACC and PSW
          LD_acc=LDEN;
        else if(sel_flags[flag_psw_sel])
         begin
          SEL_psw=SEL_PSW_DATA;
          LD_psw=LDEN;
         end
        else
         begin
          SEL_gr_addr=SEL_GR_ADDR_RRR;
          LD_gr6=LDEN;
         end
        SC_clr_n=1'b0;
       end
      default:SC_clr_n=1'b0;
     endcase
    end

    NOP :         //Opcode NOP
     SC_clr_n=1'b0;
   default :      //默认/无效状态处理
     SC_clr_n=1'b0;
  endcase
  end

end

endmodule