datapath.v

这个是用可编程器件进行仿真CPU的程序

//**************************************************
//** Revision    :  0.1
//** File name   :  datapath.v
//** Module name :  datapath
//** Discription :  The datapath of the Taocore
//** Simulator   :  Quartus II 5.1 web edition
//** Synthesizer :  Quartus II 5.1 web edition
//** Author      :  IamFree
//** Last modified:    @ 2006///
//** Created date:  2006/03/08
//**************************************************

/***************************************************
** Below is the modules that used in the datapath
***************************************************
module reg3(Dout,Din,rst_n,clk,ld);
module reg8(Dout,Din,rst_n,clk,ld);
module GR6(Dout,ACC_sel,PSW_sel,Din,clk,ld,GR6_address);
module add_one11(a1_O,a1_I);
module sub_one11(s1_O,s1_I);
module ALU(ALU_O,ALU_Co,ALU_P,ALU_Z,ALU_Ci,ALU_Op,ALU_A,ALU_B);
module mux3x2(mux_out,mux_sel,mux_a,mux_b);
module mux3x3(mux_out,mux_sel,mux_a,mux_b,mux_c);
module mux8x3(mux_out,mux_sel,mux_a,mux_b,mux_c);
module mux8x4(mux_out,mux_sel,mux_a,mux_b,mux_c,mux_d);
module mux11x3(mux_out,mux_sel,mux_a,mux_b,mux_c);
module mux11x2(mux_out,mux_sel,mux_a,mux_b);
***************************************************/


module datapath(
//outputs
address,         //Memory address
opcode,          //Opcode that send to CU
flags,           //Flags in PSW
sel_flags,       //ACC,PSW addressing signal
//inputs
sys_clk,         //System clock
sys_rst,         //System reset
alu_func,        //ALU function select

LD_acc,          //All the port names that start with "LD_"
LD_arl,          //are registers' loadable signals.
LD_pcl,
LD_ir ,
LD_spl,
LD_sph,
LD_arh,
LD_pch,
LD_psw,
LD_gr6,

SEL_arh,         //All the port names that start with "SEL_"
SEL_gr_addr,     //are MUXs' selection signals.
SEL_psw,
SEL_alu,
SEL_sp,
SEL_databus,
SEL_pc,
SEL_address,

data_in,
data_out
);

//Parameter define
parameter width=8;          //Data bus's width
parameter BX_ADDR=3'b001;   //Base register BX's address in GR6
parameter address_width=11;
parameter flag_acc_sel=1;
parameter flag_psw_sel=0;

//Port define
output [1:0] sel_flags;
output [4:0] opcode;
output [2:0] flags;
output [address_width-1:0] address;

input sys_clk;
input sys_rst;
input [4:0] alu_func;

input LD_acc;  //Loadable signals
input LD_arl;
input LD_pcl;
input LD_ir ;
input LD_spl;
input LD_sph;
input LD_arh;
input LD_pch;
input LD_psw;
input LD_gr6;

input SEL_arh; //Selection signals
input SEL_gr_addr;
input SEL_psw;
input [1:0] SEL_alu;
input [1:0] SEL_sp;
input [1:0] SEL_databus;
input SEL_pc;
input [1:0] SEL_address;


//Port type
input  [width-1:0] data_in;
output [width-1:0] data_out;

//Internal wire defination
wire [width-1:0] data_bus;

wire [width-1:0] acc2alu ;
wire [width-1:0] mux2alu;
wire [width-1:0] gr2mux;
wire [2:0]       mux2gr;
wire [width-1:0] alu2mux;
wire [2:0]       pch2mux;
wire [width-1:0] pcl2mux;
wire [2:0]       sph2mux;
wire [width-1:0] spl2mux;
wire [2:0]       arh2mux;
wire [width-1:0] arl2mux;
wire [2:0]       mux2sph;
wire [width-1:0] mux2spl;
wire [2:0]       mux2arh;
wire [2:0]       rrr2mux;
wire [2:0]       mux2psw;
wire [2:0]       flags2mux;
wire [width-1:0] irout;

wire [address_width-1:0] sp_s12mux;
wire [address_width-1:0] sp_a12mux;
wire [address_width-1:0] pca12mux;
wire [address_width-1:0] mux2pc;

//Body
//Opcode
assign opcode=irout[width-1:width-5];
assign rrr2mux=irout[2:0];

//Data bus
assign data_out=data_bus;

//The internal registers
reg8 ACC(.Dout(acc2alu),.Din(data_bus),.rst_n(sys_rst),.clk(sys_clk),.ld(LD_acc));
reg8 ARL(.Dout(arl2mux),.Din(data_bus),.rst_n(sys_rst),.clk(sys_clk),.ld(LD_arl));

reg8 PCL(.Dout(pcl2mux),.Din(mux2pc[width-1:0]),.rst_n(sys_rst),.clk(sys_clk),.ld(LD_pcl));

reg8 SPL(.Dout(spl2mux),.Din(mux2spl) ,.rst_n(sys_rst),.clk(sys_clk),.ld(LD_spl));

reg8 IR (.Dout(irout)  ,.Din(data_in) ,.rst_n(sys_rst),.clk(sys_clk),.ld(LD_ir));

reg3 ARH(.Dout(arh2mux),.Din(mux2arh),.rst_n(sys_rst),.clk(sys_clk),.ld(LD_arh));

reg3 SPH(.Dout(sph2mux),.Din(mux2sph),.rst_n(sys_rst),.clk(sys_clk),.ld(LD_sph));
reg3 PCH(.Dout(pch2mux),.Din(mux2pc[address_width-1 : address_width-3]),.rst_n(sys_rst),.clk(sys_clk),.ld(LD_pch));
reg3 PSW(.Dout(flags),.Din(mux2psw),.rst_n(sys_rst),.clk(sys_clk),.ld(LD_psw));

//GR6 general porpus register
GR6  mgr(.Dout(gr2mux),.ACC_sel(sel_flags[flag_acc_sel]),.PSW_sel(sel_flags[flag_psw_sel]),
         .Din(data_bus),.clk(sys_clk),.ld(LD_gr6),.GR6_address(mux2gr));

//ALU
ALU  malu(.ALU_O(alu2mux),.ALU_Co(flags2mux[0]),.ALU_P(flags2mux[2]),.ALU_Z(flags2mux[1]),.ALU_Ci(flags[0]),
          .ALU_Op(alu_func),.ALU_A(acc2alu),.ALU_B(mux2alu));

//The internal muxs
mux3x2  To_arh(.mux_out(mux2arh),.mux_sel(SEL_arh),.mux_a(rrr2mux),.mux_b(data_bus[2:0]));

mux3x2  To_GR_addr(.mux_out(mux2gr),.mux_sel(SEL_gr_addr),.mux_a(rrr2mux),.mux_b(BX_ADDR));
mux3x2  To_psw(.mux_out(mux2psw),.mux_sel(SEL_psw),.mux_a(flags2mux),.mux_b(data_bus[2:0]));

mux3x3  To_sph(.mux_out(mux2sph),.mux_sel(SEL_sp),.mux_a(sp_s12mux[address_width-1:address_width-3]),
               .mux_b(sp_a12mux[address_width-1:address_width-3]),.mux_c(data_bus[2:0]));

mux8x3  To_Alu_B(.mux_out(mux2alu),.mux_sel(SEL_alu),.mux_a(data_in),.mux_b(gr2mux),.mux_c({5'b00000,flags}));

mux8x3  To_spl(.mux_out(mux2spl),.mux_sel(SEL_sp),.mux_a(sp_s12mux[width-1:0]),
               .mux_b(sp_a12mux[width-1:0]),.mux_c(data_bus));

mux8x3  To_databus(.mux_out(data_bus),.mux_sel(SEL_databus),.mux_a(pcl2mux),
                   .mux_b({5'b00000,pch2mux}),.mux_c(alu2mux));

mux11x2 To_pc(.mux_out(mux2pc),.mux_sel(SEL_pc),.mux_a(pca12mux),.mux_b({arh2mux,arl2mux}));

mux11x3 To_address(.mux_out(address),.mux_sel(SEL_address),.mux_a({pch2mux,pcl2mux}),
                   .mux_b({arh2mux,arl2mux}),.mux_c({sph2mux,spl2mux}));

//The a1 and s1
add_one11 Pc_a1(.a1_O(pca12mux) ,.a1_I({pch2mux,pcl2mux}));
add_one11 Sp_a1(.a1_O(sp_a12mux),.a1_I({sph2mux,spl2mux}));
sub_one11 Sp_s1(.s1_O(sp_s12mux),.s1_I({sph2mux,spl2mux}));

endmodule