ddr1_test.ucf

xinlinx s vhdl code model and user guider

##  constraints for bit ddr1_dq, 23
INST "ddr1_dq(23)" LOC = P5;
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit23/fbit0" RLOC = X0Y1;
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit23/fbit0" BEL = "FFX";
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit23/fbit0" U_SET = "ddr1_top0/data_path0/data_read0/ddr1_dqbit22/dq";
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit23/fbit2" RLOC = X1Y1;
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit23/fbit2" BEL = "FFX";
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit23/fbit2" U_SET = "ddr1_top0/data_path0/data_read0/ddr1_dqbit22/dq";
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit23/fbit1" RLOC = X3Y1;
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit23/fbit1" BEL = "FFX";
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit23/fbit1" U_SET = "ddr1_top0/data_path0/data_read0/ddr1_dqbit22/dq";
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit23/fbit3" RLOC = X2Y1;
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit23/fbit3" BEL = "FFX";
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit23/fbit3" U_SET = "ddr1_top0/data_path0/data_read0/ddr1_dqbit22/dq";

#############################################################
##  constraints for bit no_dpin, 2
INST "ddr1_top0/data_path0/data_read_controller0/ddr1_dqs_div2/col0" LOC = SLICE_X91Y75;
INST "ddr1_top0/data_path0/data_read_controller0/ddr1_dqs_div2/col1" LOC = SLICE_X89Y75;
NET "ddr1_top0/data_path0/data_read_controller0/ddr1_dqs_div2/dqs_divn" MAXDELAY = 1200ps;
NET "ddr1_top0/data_path0/data_read_controller0/ddr1_dqs_div2/dqs_divp" MAXDELAY = 1200ps;
INST "ddr1_top0/data_path0/data_read_controller0/ddr1_transfer_done2/xdone0_clk0" LOC = SLICE_X89Y74;
INST "ddr1_top0/data_path0/data_read_controller0/ddr1_transfer_done2/xdone0_clk0" BEL = FFX;
INST "ddr1_top0/data_path0/data_read_controller0/ddr1_transfer_done2/xdone0_clk90" LOC = SLICE_X91Y74;
INST "ddr1_top0/data_path0/data_read_controller0/ddr1_transfer_done2/xdone0_clk90" BEL = FFX;
INST "ddr1_top0/data_path0/data_read_controller0/ddr1_transfer_done2/xdone0_rst90" LOC = SLICE_X91Y74;
INST "ddr1_top0/data_path0/data_read_controller0/ddr1_transfer_done2/xdone0_rst90" BEL = G;
INST "ddr1_top0/data_path0/data_read_controller0/ddr1_transfer_done2/xdone0_clk180" LOC = SLICE_X88Y75;
INST "ddr1_top0/data_path0/data_read_controller0/ddr1_transfer_done2/xdone0_clk180" BEL = FFX;
INST "ddr1_top0/data_path0/data_read_controller0/ddr1_transfer_done2/xdone0_clk270" LOC = SLICE_X90Y75;
INST "ddr1_top0/data_path0/data_read_controller0/ddr1_transfer_done2/xdone0_clk270" BEL = FFX;
INST "ddr1_top0/data_path0/data_read_controller0/ddr1_transfer_done2/xdone0_rst270" LOC = SLICE_X90Y75;
INST "ddr1_top0/data_path0/data_read_controller0/ddr1_transfer_done2/xdone0_rst270" BEL = G;
INST "ddr1_top0/data_path0/data_read_controller0/ddr1_transfer_done2/xdone0" LOC = SLICE_X90Y75;
INST "ddr1_top0/data_path0/data_read_controller0/ddr1_transfer_done2/xdone0" BEL = F;

INST "ddr1_top0/data_path0/data_read_controller0/ddr1_transfer_done2/xdone1_clk270" LOC = SLICE_X87Y75;
INST "ddr1_top0/data_path0/data_read_controller0/ddr1_transfer_done2/xdone1_clk270" BEL = FFX;
INST "ddr1_top0/data_path0/data_read_controller0/ddr1_transfer_done2/xdone2_clk270" LOC = SLICE_X87Y75;
INST "ddr1_top0/data_path0/data_read_controller0/ddr1_transfer_done2/xdone2_clk270" BEL = FFY;
INST "ddr1_top0/data_path0/data_read_controller0/ddr1_transfer_done2/xdone1_clk90" LOC = SLICE_X87Y74;
INST "ddr1_top0/data_path0/data_read_controller0/ddr1_transfer_done2/xdone1_clk90" BEL = FFX;
INST "ddr1_top0/data_path0/data_read_controller0/ddr1_transfer_done2/xdone2_clk90" LOC = SLICE_X87Y74;
INST "ddr1_top0/data_path0/data_read_controller0/ddr1_transfer_done2/xdone2_clk90" BEL = FFY;
INST "ddr1_top0/data_path0/data_read_controller0/ddr1_transfer_done2/xdone1" LOC = SLICE_X87Y74;
INST "ddr1_top0/data_path0/data_read_controller0/ddr1_transfer_done2/xdone1" BEL = F;
INST "ddr1_top0/data_path0/data_read_controller0/ddr1_transfer_done2/xdone2" LOC = SLICE_X87Y74;
INST "ddr1_top0/data_path0/data_read_controller0/ddr1_transfer_done2/xdone2" BEL = G;
INST "ddr1_top0/data_path0/data_read_controller0/ddr1_transfer_done2/xdone3_clk90" LOC = SLICE_X86Y75;
INST "ddr1_top0/data_path0/data_read_controller0/ddr1_transfer_done2/xdone3_clk90" BEL = FFX;
INST "ddr1_top0/data_path0/data_read_controller0/ddr1_transfer_done2/xdone3_clk270" LOC = SLICE_X86Y74;
INST "ddr1_top0/data_path0/data_read_controller0/ddr1_transfer_done2/xdone3_clk270" BEL = FFX;
INST "ddr1_top0/data_path0/data_read_controller0/ddr1_transfer_done2/xdone3" LOC = SLICE_X86Y74;
INST "ddr1_top0/data_path0/data_read_controller0/ddr1_transfer_done2/xdone3" BEL = F;
#############################################################
##  constraints for bit ddr1_dqs, 3
INST "ddr1_dqs(3)" LOC = R1;
## LUT location constraints for col 0
INST "ddr1_top0/data_path0/data_read_controller0/dqs_delay3_col0/one" LOC = SLICE_X90Y70;
INST "ddr1_top0/data_path0/data_read_controller0/dqs_delay3_col0/one" BEL = F;
INST "ddr1_top0/data_path0/data_read_controller0/dqs_delay3_col0/two" LOC = SLICE_X90Y71;
INST "ddr1_top0/data_path0/data_read_controller0/dqs_delay3_col0/two" BEL = F;
INST "ddr1_top0/data_path0/data_read_controller0/dqs_delay3_col0/three" LOC = SLICE_X90Y71;
INST "ddr1_top0/data_path0/data_read_controller0/dqs_delay3_col0/three" BEL = G;
INST "ddr1_top0/data_path0/data_read_controller0/dqs_delay3_col0/four" LOC = SLICE_X91Y70;
INST "ddr1_top0/data_path0/data_read_controller0/dqs_delay3_col0/four" BEL = F;
INST "ddr1_top0/data_path0/data_read_controller0/dqs_delay3_col0/five" LOC = SLICE_X91Y70;
INST "ddr1_top0/data_path0/data_read_controller0/dqs_delay3_col0/five" BEL = G;
INST "ddr1_top0/data_path0/data_read_controller0/dqs_delay3_col0/six" LOC = SLICE_X91Y71;
INST "ddr1_top0/data_path0/data_read_controller0/dqs_delay3_col0/six" BEL = G;

## LUT location constraints for col 1
INST "ddr1_top0/data_path0/data_read_controller0/dqs_delay3_col1/one" LOC = SLICE_X88Y70;
INST "ddr1_top0/data_path0/data_read_controller0/dqs_delay3_col1/one" BEL = F;
INST "ddr1_top0/data_path0/data_read_controller0/dqs_delay3_col1/two" LOC = SLICE_X88Y71;
INST "ddr1_top0/data_path0/data_read_controller0/dqs_delay3_col1/two" BEL = F;
INST "ddr1_top0/data_path0/data_read_controller0/dqs_delay3_col1/three" LOC = SLICE_X88Y71;
INST "ddr1_top0/data_path0/data_read_controller0/dqs_delay3_col1/three" BEL = G;
INST "ddr1_top0/data_path0/data_read_controller0/dqs_delay3_col1/four" LOC = SLICE_X89Y70;
INST "ddr1_top0/data_path0/data_read_controller0/dqs_delay3_col1/four" BEL = F;
INST "ddr1_top0/data_path0/data_read_controller0/dqs_delay3_col1/five" LOC = SLICE_X89Y70;
INST "ddr1_top0/data_path0/data_read_controller0/dqs_delay3_col1/five" BEL = G;
INST "ddr1_top0/data_path0/data_read_controller0/dqs_delay3_col1/six" LOC = SLICE_X89Y71;
INST "ddr1_top0/data_path0/data_read_controller0/dqs_delay3_col1/six" BEL = G;
#############################################################
##  constraints for bit ddr1_dq, 24
INST "ddr1_dq(24)" LOC = R4;
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit24/fbit0" RLOC_ORIGIN = X88Y68;
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit24/fbit0" RLOC = X0Y1;
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit24/fbit0" BEL = "FFY";
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit24/fbit0" U_SET = "ddr1_top0/data_path0/data_read0/ddr1_dqbit24/dq";
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit24/fbit2" RLOC = X1Y1;
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit24/fbit2" BEL = "FFY";
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit24/fbit2" U_SET = "ddr1_top0/data_path0/data_read0/ddr1_dqbit24/dq";
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit24/fbit1" RLOC = X3Y1;
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit24/fbit1" BEL = "FFY";
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit24/fbit1" U_SET = "ddr1_top0/data_path0/data_read0/ddr1_dqbit24/dq";
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit24/fbit3" RLOC = X2Y1;
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit24/fbit3" BEL = "FFY";
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit24/fbit3" U_SET = "ddr1_top0/data_path0/data_read0/ddr1_dqbit24/dq";
#############################################################
##  constraints for bit ddr1_dq, 25
INST "ddr1_dq(25)" LOC = R3;
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit25/fbit0" RLOC = X0Y1;
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit25/fbit0" BEL = "FFX";
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit25/fbit0" U_SET = "ddr1_top0/data_path0/data_read0/ddr1_dqbit24/dq";
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit25/fbit2" RLOC = X1Y1;
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit25/fbit2" BEL = "FFX";
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit25/fbit2" U_SET = "ddr1_top0/data_path0/data_read0/ddr1_dqbit24/dq";
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit25/fbit1" RLOC = X3Y1;
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit25/fbit1" BEL = "FFX";
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit25/fbit1" U_SET = "ddr1_top0/data_path0/data_read0/ddr1_dqbit24/dq";
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit25/fbit3" RLOC = X2Y1;
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit25/fbit3" BEL = "FFX";
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit25/fbit3" U_SET = "ddr1_top0/data_path0/data_read0/ddr1_dqbit24/dq";

#############################################################
##  constraints for bit ddr1_dq, 26
INST "ddr1_dq(26)" LOC = T2;
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit26/fbit0" RLOC_ORIGIN = X88Y66;
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit26/fbit0" RLOC = X0Y0;
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit26/fbit0" BEL = "FFY";
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit26/fbit0" U_SET = "ddr1_top0/data_path0/data_read0/ddr1_dqbit26/dq";
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit26/fbit2" RLOC = X1Y0;
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit26/fbit2" BEL = "FFY";
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit26/fbit2" U_SET = "ddr1_top0/data_path0/data_read0/ddr1_dqbit26/dq";
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit26/fbit1" RLOC = X3Y0;
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit26/fbit1" BEL = "FFY";
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit26/fbit1" U_SET = "ddr1_top0/data_path0/data_read0/ddr1_dqbit26/dq";
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit26/fbit3" RLOC = X2Y0;
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit26/fbit3" BEL = "FFY";
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit26/fbit3" U_SET = "ddr1_top0/data_path0/data_read0/ddr1_dqbit26/dq";
#############################################################
##  constraints for bit ddr1_dq, 27
INST "ddr1_dq(27)" LOC = T8;
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit27/fbit0" RLOC = X0Y1;
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit27/fbit0" BEL = "FFY";
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit27/fbit0" U_SET = "ddr1_top0/data_path0/data_read0/ddr1_dqbit26/dq";
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit27/fbit2" RLOC = X1Y1;
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit27/fbit2" BEL = "FFY";
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit27/fbit2" U_SET = "ddr1_top0/data_path0/data_read0/ddr1_dqbit26/dq";
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit27/fbit1" RLOC = X3Y1;
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit27/fbit1" BEL = "FFY";
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit27/fbit1" U_SET = "ddr1_top0/data_path0/data_read0/ddr1_dqbit26/dq";
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit27/fbit3" RLOC = X2Y1;
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit27/fbit3" BEL = "FFY";
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit27/fbit3" U_SET = "ddr1_top0/data_path0/data_read0/ddr1_dqbit26/dq";
#############################################################
##  constraints for bit ddr1_dq, 28
INST "ddr1_dq(28)" LOC = T7;
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit28/fbit0" RLOC = X0Y1;
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit28/fbit0" BEL = "FFX";
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit28/fbit0" U_SET = "ddr1_top0/data_path0/data_read0/ddr1_dqbit26/dq";
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit28/fbit2" RLOC = X1Y1;
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit28/fbit2" BEL = "FFX";
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit28/fbit2" U_SET = "ddr1_top0/data_path0/data_read0/ddr1_dqbit26/dq";
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit28/fbit1" RLOC = X3Y1;
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit28/fbit1" BEL = "FFX";
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit28/fbit1" U_SET = "ddr1_top0/data_path0/data_read0/ddr1_dqbit26/dq";
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit28/fbit3" RLOC = X2Y1;
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit28/fbit3" BEL = "FFX";
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit28/fbit3" U_SET = "ddr1_top0/data_path0/data_read0/ddr1_dqbit26/dq";

#############################################################
##  constraints for bit ddr1_dq, 29
INST "ddr1_dq(29)" LOC = T6;
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit29/fbit0" RLOC_ORIGIN = X88Y64;
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit29/fbit0" RLOC = X0Y1;
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit29/fbit0" BEL = "FFY";
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit29/fbit0" U_SET = "ddr1_top0/data_path0/data_read0/ddr1_dqbit29/dq";
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit29/fbit2" RLOC = X1Y1;
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit29/fbit2" BEL = "FFY";
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit29/fbit2" U_SET = "ddr1_top0/data_path0/data_read0/ddr1_dqbit29/dq";
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit29/fbit1" RLOC = X3Y1;
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit29/fbit1" BEL = "FFY";
INST "ddr1_to