ddr1_test.ucf

xinlinx s vhdl code model and user guider

##  constraints for bit no_dpin, 1
INST "ddr1_top0/data_path0/data_read_controller0/ddr1_dqs_div1/col0" LOC = SLICE_X91Y85;
INST "ddr1_top0/data_path0/data_read_controller0/ddr1_dqs_div1/col1" LOC = SLICE_X89Y85;
NET "ddr1_top0/data_path0/data_read_controller0/ddr1_dqs_div1/dqs_divn" MAXDELAY = 1200ps;
NET "ddr1_top0/data_path0/data_read_controller0/ddr1_dqs_div1/dqs_divp" MAXDELAY = 1200ps;
INST "ddr1_top0/data_path0/data_read_controller0/ddr1_transfer_done1/xdone0_clk0" LOC = SLICE_X89Y84;
INST "ddr1_top0/data_path0/data_read_controller0/ddr1_transfer_done1/xdone0_clk0" BEL = FFX;
INST "ddr1_top0/data_path0/data_read_controller0/ddr1_transfer_done1/xdone0_clk90" LOC = SLICE_X91Y84;
INST "ddr1_top0/data_path0/data_read_controller0/ddr1_transfer_done1/xdone0_clk90" BEL = FFX;
INST "ddr1_top0/data_path0/data_read_controller0/ddr1_transfer_done1/xdone0_rst90" LOC = SLICE_X91Y84;
INST "ddr1_top0/data_path0/data_read_controller0/ddr1_transfer_done1/xdone0_rst90" BEL = G;
INST "ddr1_top0/data_path0/data_read_controller0/ddr1_transfer_done1/xdone0_clk180" LOC = SLICE_X88Y85;
INST "ddr1_top0/data_path0/data_read_controller0/ddr1_transfer_done1/xdone0_clk180" BEL = FFX;
INST "ddr1_top0/data_path0/data_read_controller0/ddr1_transfer_done1/xdone0_clk270" LOC = SLICE_X90Y85;
INST "ddr1_top0/data_path0/data_read_controller0/ddr1_transfer_done1/xdone0_clk270" BEL = FFX;
INST "ddr1_top0/data_path0/data_read_controller0/ddr1_transfer_done1/xdone0_rst270" LOC = SLICE_X90Y85;
INST "ddr1_top0/data_path0/data_read_controller0/ddr1_transfer_done1/xdone0_rst270" BEL = G;
INST "ddr1_top0/data_path0/data_read_controller0/ddr1_transfer_done1/xdone0" LOC = SLICE_X90Y85;
INST "ddr1_top0/data_path0/data_read_controller0/ddr1_transfer_done1/xdone0" BEL = F;

INST "ddr1_top0/data_path0/data_read_controller0/ddr1_transfer_done1/xdone1_clk270" LOC = SLICE_X87Y85;
INST "ddr1_top0/data_path0/data_read_controller0/ddr1_transfer_done1/xdone1_clk270" BEL = FFX;
INST "ddr1_top0/data_path0/data_read_controller0/ddr1_transfer_done1/xdone2_clk270" LOC = SLICE_X87Y85;
INST "ddr1_top0/data_path0/data_read_controller0/ddr1_transfer_done1/xdone2_clk270" BEL = FFY;
INST "ddr1_top0/data_path0/data_read_controller0/ddr1_transfer_done1/xdone1_clk90" LOC = SLICE_X87Y84;
INST "ddr1_top0/data_path0/data_read_controller0/ddr1_transfer_done1/xdone1_clk90" BEL = FFX;
INST "ddr1_top0/data_path0/data_read_controller0/ddr1_transfer_done1/xdone2_clk90" LOC = SLICE_X87Y84;
INST "ddr1_top0/data_path0/data_read_controller0/ddr1_transfer_done1/xdone2_clk90" BEL = FFY;
INST "ddr1_top0/data_path0/data_read_controller0/ddr1_transfer_done1/xdone1" LOC = SLICE_X87Y84;
INST "ddr1_top0/data_path0/data_read_controller0/ddr1_transfer_done1/xdone1" BEL = F;
INST "ddr1_top0/data_path0/data_read_controller0/ddr1_transfer_done1/xdone2" LOC = SLICE_X87Y84;
INST "ddr1_top0/data_path0/data_read_controller0/ddr1_transfer_done1/xdone2" BEL = G;
INST "ddr1_top0/data_path0/data_read_controller0/ddr1_transfer_done1/xdone3_clk90" LOC = SLICE_X86Y85;
INST "ddr1_top0/data_path0/data_read_controller0/ddr1_transfer_done1/xdone3_clk90" BEL = FFX;
INST "ddr1_top0/data_path0/data_read_controller0/ddr1_transfer_done1/xdone3_clk270" LOC = SLICE_X86Y84;
INST "ddr1_top0/data_path0/data_read_controller0/ddr1_transfer_done1/xdone3_clk270" BEL = FFX;
INST "ddr1_top0/data_path0/data_read_controller0/ddr1_transfer_done1/xdone3" LOC = SLICE_X86Y84;
INST "ddr1_top0/data_path0/data_read_controller0/ddr1_transfer_done1/xdone3" BEL = F;
#############################################################
##  constraints for bit ddr1_dqs, 2
INST "ddr1_dqs(2)" LOC = N1;
## LUT location constraints for col 0
INST "ddr1_top0/data_path0/data_read_controller0/dqs_delay2_col0/one" LOC = SLICE_X90Y82;
INST "ddr1_top0/data_path0/data_read_controller0/dqs_delay2_col0/one" BEL = F;
INST "ddr1_top0/data_path0/data_read_controller0/dqs_delay2_col0/two" LOC = SLICE_X90Y83;
INST "ddr1_top0/data_path0/data_read_controller0/dqs_delay2_col0/two" BEL = F;
INST "ddr1_top0/data_path0/data_read_controller0/dqs_delay2_col0/three" LOC = SLICE_X90Y83;
INST "ddr1_top0/data_path0/data_read_controller0/dqs_delay2_col0/three" BEL = G;
INST "ddr1_top0/data_path0/data_read_controller0/dqs_delay2_col0/four" LOC = SLICE_X91Y82;
INST "ddr1_top0/data_path0/data_read_controller0/dqs_delay2_col0/four" BEL = F;
INST "ddr1_top0/data_path0/data_read_controller0/dqs_delay2_col0/five" LOC = SLICE_X91Y82;
INST "ddr1_top0/data_path0/data_read_controller0/dqs_delay2_col0/five" BEL = G;
INST "ddr1_top0/data_path0/data_read_controller0/dqs_delay2_col0/six" LOC = SLICE_X91Y83;
INST "ddr1_top0/data_path0/data_read_controller0/dqs_delay2_col0/six" BEL = G;

## LUT location constraints for col 1
INST "ddr1_top0/data_path0/data_read_controller0/dqs_delay2_col1/one" LOC = SLICE_X88Y82;
INST "ddr1_top0/data_path0/data_read_controller0/dqs_delay2_col1/one" BEL = F;
INST "ddr1_top0/data_path0/data_read_controller0/dqs_delay2_col1/two" LOC = SLICE_X88Y83;
INST "ddr1_top0/data_path0/data_read_controller0/dqs_delay2_col1/two" BEL = F;
INST "ddr1_top0/data_path0/data_read_controller0/dqs_delay2_col1/three" LOC = SLICE_X88Y83;
INST "ddr1_top0/data_path0/data_read_controller0/dqs_delay2_col1/three" BEL = G;
INST "ddr1_top0/data_path0/data_read_controller0/dqs_delay2_col1/four" LOC = SLICE_X89Y82;
INST "ddr1_top0/data_path0/data_read_controller0/dqs_delay2_col1/four" BEL = F;
INST "ddr1_top0/data_path0/data_read_controller0/dqs_delay2_col1/five" LOC = SLICE_X89Y82;
INST "ddr1_top0/data_path0/data_read_controller0/dqs_delay2_col1/five" BEL = G;
INST "ddr1_top0/data_path0/data_read_controller0/dqs_delay2_col1/six" LOC = SLICE_X89Y83;
INST "ddr1_top0/data_path0/data_read_controller0/dqs_delay2_col1/six" BEL = G;
#############################################################
##  constraints for bit ddr1_dq, 16
INST "ddr1_dq(16)" LOC = N4;
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit16/fbit0" RLOC_ORIGIN = X88Y80;
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit16/fbit0" RLOC = X0Y1;
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit16/fbit0" BEL = "FFY";
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit16/fbit0" U_SET = "ddr1_top0/data_path0/data_read0/ddr1_dqbit16/dq";
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit16/fbit2" RLOC = X1Y1;
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit16/fbit2" BEL = "FFY";
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit16/fbit2" U_SET = "ddr1_top0/data_path0/data_read0/ddr1_dqbit16/dq";
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit16/fbit1" RLOC = X3Y1;
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit16/fbit1" BEL = "FFY";
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit16/fbit1" U_SET = "ddr1_top0/data_path0/data_read0/ddr1_dqbit16/dq";
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit16/fbit3" RLOC = X2Y1;
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit16/fbit3" BEL = "FFY";
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit16/fbit3" U_SET = "ddr1_top0/data_path0/data_read0/ddr1_dqbit16/dq";
#############################################################
##  constraints for bit ddr1_dq, 17
INST "ddr1_dq(17)" LOC = N3;
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit17/fbit0" RLOC = X0Y1;
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit17/fbit0" BEL = "FFX";
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit17/fbit0" U_SET = "ddr1_top0/data_path0/data_read0/ddr1_dqbit16/dq";
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit17/fbit2" RLOC = X1Y1;
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit17/fbit2" BEL = "FFX";
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit17/fbit2" U_SET = "ddr1_top0/data_path0/data_read0/ddr1_dqbit16/dq";
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit17/fbit1" RLOC = X3Y1;
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit17/fbit1" BEL = "FFX";
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit17/fbit1" U_SET = "ddr1_top0/data_path0/data_read0/ddr1_dqbit16/dq";
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit17/fbit3" RLOC = X2Y1;
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit17/fbit3" BEL = "FFX";
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit17/fbit3" U_SET = "ddr1_top0/data_path0/data_read0/ddr1_dqbit16/dq";

#############################################################
##  constraints for bit ddr1_dq, 18
INST "ddr1_dq(18)" LOC = N2;
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit18/fbit0" RLOC_ORIGIN = X88Y78;
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit18/fbit0" RLOC = X0Y0;
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit18/fbit0" BEL = "FFX";
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit18/fbit0" U_SET = "ddr1_top0/data_path0/data_read0/ddr1_dqbit18/dq";
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit18/fbit2" RLOC = X1Y0;
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit18/fbit2" BEL = "FFX";
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit18/fbit2" U_SET = "ddr1_top0/data_path0/data_read0/ddr1_dqbit18/dq";
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit18/fbit1" RLOC = X3Y0;
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit18/fbit1" BEL = "FFX";
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit18/fbit1" U_SET = "ddr1_top0/data_path0/data_read0/ddr1_dqbit18/dq";
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit18/fbit3" RLOC = X2Y0;
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit18/fbit3" BEL = "FFX";
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit18/fbit3" U_SET = "ddr1_top0/data_path0/data_read0/ddr1_dqbit18/dq";
#############################################################
##  constraints for bit ddr1_dq, 19
INST "ddr1_dq(19)" LOC = P2;
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit19/fbit0" RLOC = X0Y0;
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit19/fbit0" BEL = "FFY";
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit19/fbit0" U_SET = "ddr1_top0/data_path0/data_read0/ddr1_dqbit18/dq";
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit19/fbit2" RLOC = X1Y0;
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit19/fbit2" BEL = "FFY";
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit19/fbit2" U_SET = "ddr1_top0/data_path0/data_read0/ddr1_dqbit18/dq";
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit19/fbit1" RLOC = X3Y0;
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit19/fbit1" BEL = "FFY";
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit19/fbit1" U_SET = "ddr1_top0/data_path0/data_read0/ddr1_dqbit18/dq";
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit19/fbit3" RLOC = X2Y0;
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit19/fbit3" BEL = "FFY";
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit19/fbit3" U_SET = "ddr1_top0/data_path0/data_read0/ddr1_dqbit18/dq";
#############################################################
##  constraints for bit ddr1_dq, 20
INST "ddr1_dq(20)" LOC = R10;
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit20/fbit0" RLOC = X0Y1;
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit20/fbit0" BEL = "FFY";
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit20/fbit0" U_SET = "ddr1_top0/data_path0/data_read0/ddr1_dqbit18/dq";
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit20/fbit2" RLOC = X1Y1;
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit20/fbit2" BEL = "FFY";
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit20/fbit2" U_SET = "ddr1_top0/data_path0/data_read0/ddr1_dqbit18/dq";
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit20/fbit1" RLOC = X3Y1;
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit20/fbit1" BEL = "FFY";
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit20/fbit1" U_SET = "ddr1_top0/data_path0/data_read0/ddr1_dqbit18/dq";
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit20/fbit3" RLOC = X2Y1;
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit20/fbit3" BEL = "FFY";
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit20/fbit3" U_SET = "ddr1_top0/data_path0/data_read0/ddr1_dqbit18/dq";
#############################################################
##  constraints for bit ddr1_dq, 21
INST "ddr1_dq(21)" LOC = R9;
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit21/fbit0" RLOC = X0Y1;
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit21/fbit0" BEL = "FFX";
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit21/fbit0" U_SET = "ddr1_top0/data_path0/data_read0/ddr1_dqbit18/dq";
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit21/fbit2" RLOC = X1Y1;
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit21/fbit2" BEL = "FFX";
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit21/fbit2" U_SET = "ddr1_top0/data_path0/data_read0/ddr1_dqbit18/dq";
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit21/fbit1" RLOC = X3Y1;
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit21/fbit1" BEL = "FFX";
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit21/fbit1" U_SET = "ddr1_top0/data_path0/data_read0/ddr1_dqbit18/dq";
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit21/fbit3" RLOC = X2Y1;
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit21/fbit3" BEL = "FFX";
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit21/fbit3" U_SET = "ddr1_top0/data_path0/data_read0/ddr1_dqbit18/dq";

#############################################################
##  constraints for bit ddr1_dq, 22
INST "ddr1_dq(22)" LOC = P6;
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit22/fbit0" RLOC_ORIGIN = X88Y76;
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit22/fbit0" RLOC = X0Y1;
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit22/fbit0" BEL = "FFY";
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit22/fbit0" U_SET = "ddr1_top0/data_path0/data_read0/ddr1_dqbit22/dq";
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit22/fbit2" RLOC = X1Y1;
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit22/fbit2" BEL = "FFY";
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit22/fbit2" U_SET = "ddr1_top0/data_path0/data_read0/ddr1_dqbit22/dq";
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit22/fbit1" RLOC = X3Y1;
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit22/fbit1" BEL = "FFY";
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit22/fbit1" U_SET = "ddr1_top0/data_path0/data_read0/ddr1_dqbit22/dq";
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit22/fbit3" RLOC = X2Y1;
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit22/fbit3" BEL = "FFY";
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit22/fbit3" U_SET = "ddr1_top0/data_path0/data_read0/ddr1_dqbit22/dq";
#############################################################