ddr1_test.ucf

xinlinx s vhdl code model and user guider

INST "ddr1_top0/data_path0/data_read_controller0/ddr1_transfer_done0/xdone0" LOC = SLICE_X90Y99;
INST "ddr1_top0/data_path0/data_read_controller0/ddr1_transfer_done0/xdone0" BEL = F;

INST "ddr1_top0/data_path0/data_read_controller0/ddr1_transfer_done0/xdone1_clk270" LOC = SLICE_X87Y99;
INST "ddr1_top0/data_path0/data_read_controller0/ddr1_transfer_done0/xdone1_clk270" BEL = FFX;
INST "ddr1_top0/data_path0/data_read_controller0/ddr1_transfer_done0/xdone2_clk270" LOC = SLICE_X87Y99;
INST "ddr1_top0/data_path0/data_read_controller0/ddr1_transfer_done0/xdone2_clk270" BEL = FFY;
INST "ddr1_top0/data_path0/data_read_controller0/ddr1_transfer_done0/xdone1_clk90" LOC = SLICE_X87Y98;
INST "ddr1_top0/data_path0/data_read_controller0/ddr1_transfer_done0/xdone1_clk90" BEL = FFX;
INST "ddr1_top0/data_path0/data_read_controller0/ddr1_transfer_done0/xdone2_clk90" LOC = SLICE_X87Y98;
INST "ddr1_top0/data_path0/data_read_controller0/ddr1_transfer_done0/xdone2_clk90" BEL = FFY;
INST "ddr1_top0/data_path0/data_read_controller0/ddr1_transfer_done0/xdone1" LOC = SLICE_X87Y98;
INST "ddr1_top0/data_path0/data_read_controller0/ddr1_transfer_done0/xdone1" BEL = F;
INST "ddr1_top0/data_path0/data_read_controller0/ddr1_transfer_done0/xdone2" LOC = SLICE_X87Y98;
INST "ddr1_top0/data_path0/data_read_controller0/ddr1_transfer_done0/xdone2" BEL = G;
INST "ddr1_top0/data_path0/data_read_controller0/ddr1_transfer_done0/xdone3_clk90" LOC = SLICE_X86Y99;
INST "ddr1_top0/data_path0/data_read_controller0/ddr1_transfer_done0/xdone3_clk90" BEL = FFX;
INST "ddr1_top0/data_path0/data_read_controller0/ddr1_transfer_done0/xdone3_clk270" LOC = SLICE_X86Y98;
INST "ddr1_top0/data_path0/data_read_controller0/ddr1_transfer_done0/xdone3_clk270" BEL = FFX;
INST "ddr1_top0/data_path0/data_read_controller0/ddr1_transfer_done0/xdone3" LOC = SLICE_X86Y98;
INST "ddr1_top0/data_path0/data_read_controller0/ddr1_transfer_done0/xdone3" BEL = F;
#############################################################
##  constraints for bit ddr1_dqs, 1
INST "ddr1_dqs(1)" LOC = L1;
## LUT location constraints for col 0
INST "ddr1_top0/data_path0/data_read_controller0/dqs_delay1_col0/one" LOC = SLICE_X90Y94;
INST "ddr1_top0/data_path0/data_read_controller0/dqs_delay1_col0/one" BEL = F;
INST "ddr1_top0/data_path0/data_read_controller0/dqs_delay1_col0/two" LOC = SLICE_X90Y95;
INST "ddr1_top0/data_path0/data_read_controller0/dqs_delay1_col0/two" BEL = F;
INST "ddr1_top0/data_path0/data_read_controller0/dqs_delay1_col0/three" LOC = SLICE_X90Y95;
INST "ddr1_top0/data_path0/data_read_controller0/dqs_delay1_col0/three" BEL = G;
INST "ddr1_top0/data_path0/data_read_controller0/dqs_delay1_col0/four" LOC = SLICE_X91Y94;
INST "ddr1_top0/data_path0/data_read_controller0/dqs_delay1_col0/four" BEL = F;
INST "ddr1_top0/data_path0/data_read_controller0/dqs_delay1_col0/five" LOC = SLICE_X91Y94;
INST "ddr1_top0/data_path0/data_read_controller0/dqs_delay1_col0/five" BEL = G;
INST "ddr1_top0/data_path0/data_read_controller0/dqs_delay1_col0/six" LOC = SLICE_X91Y95;
INST "ddr1_top0/data_path0/data_read_controller0/dqs_delay1_col0/six" BEL = G;

## LUT location constraints for col 1
INST "ddr1_top0/data_path0/data_read_controller0/dqs_delay1_col1/one" LOC = SLICE_X88Y94;
INST "ddr1_top0/data_path0/data_read_controller0/dqs_delay1_col1/one" BEL = F;
INST "ddr1_top0/data_path0/data_read_controller0/dqs_delay1_col1/two" LOC = SLICE_X88Y95;
INST "ddr1_top0/data_path0/data_read_controller0/dqs_delay1_col1/two" BEL = F;
INST "ddr1_top0/data_path0/data_read_controller0/dqs_delay1_col1/three" LOC = SLICE_X88Y95;
INST "ddr1_top0/data_path0/data_read_controller0/dqs_delay1_col1/three" BEL = G;
INST "ddr1_top0/data_path0/data_read_controller0/dqs_delay1_col1/four" LOC = SLICE_X89Y94;
INST "ddr1_top0/data_path0/data_read_controller0/dqs_delay1_col1/four" BEL = F;
INST "ddr1_top0/data_path0/data_read_controller0/dqs_delay1_col1/five" LOC = SLICE_X89Y94;
INST "ddr1_top0/data_path0/data_read_controller0/dqs_delay1_col1/five" BEL = G;
INST "ddr1_top0/data_path0/data_read_controller0/dqs_delay1_col1/six" LOC = SLICE_X89Y95;
INST "ddr1_top0/data_path0/data_read_controller0/dqs_delay1_col1/six" BEL = G;
#############################################################
##  constraints for bit ddr1_dq, 8
INST "ddr1_dq(8)" LOC = M7;
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit8/fbit0" RLOC_ORIGIN = X88Y92;
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit8/fbit0" RLOC = X0Y1;
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit8/fbit0" BEL = "FFY";
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit8/fbit0" U_SET = "ddr1_top0/data_path0/data_read0/ddr1_dqbit8/dq";
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit8/fbit2" RLOC = X1Y1;
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit8/fbit2" BEL = "FFY";
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit8/fbit2" U_SET = "ddr1_top0/data_path0/data_read0/ddr1_dqbit8/dq";
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit8/fbit1" RLOC = X3Y1;
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit8/fbit1" BEL = "FFY";
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit8/fbit1" U_SET = "ddr1_top0/data_path0/data_read0/ddr1_dqbit8/dq";
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit8/fbit3" RLOC = X2Y1;
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit8/fbit3" BEL = "FFY";
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit8/fbit3" U_SET = "ddr1_top0/data_path0/data_read0/ddr1_dqbit8/dq";
#############################################################
##  constraints for bit ddr1_dq, 9
INST "ddr1_dq(9)" LOC = M6;
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit9/fbit0" RLOC = X0Y1;
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit9/fbit0" BEL = "FFX";
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit9/fbit0" U_SET = "ddr1_top0/data_path0/data_read0/ddr1_dqbit8/dq";
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit9/fbit2" RLOC = X1Y1;
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit9/fbit2" BEL = "FFX";
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit9/fbit2" U_SET = "ddr1_top0/data_path0/data_read0/ddr1_dqbit8/dq";
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit9/fbit1" RLOC = X3Y1;
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit9/fbit1" BEL = "FFX";
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit9/fbit1" U_SET = "ddr1_top0/data_path0/data_read0/ddr1_dqbit8/dq";
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit9/fbit3" RLOC = X2Y1;
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit9/fbit3" BEL = "FFX";
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit9/fbit3" U_SET = "ddr1_top0/data_path0/data_read0/ddr1_dqbit8/dq";

#############################################################
##  constraints for bit ddr1_dq, 10
INST "ddr1_dq(10)" LOC = M2;
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit10/fbit0" RLOC_ORIGIN = X88Y90;
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit10/fbit0" RLOC = X0Y0;
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit10/fbit0" BEL = "FFY";
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit10/fbit0" U_SET = "ddr1_top0/data_path0/data_read0/ddr1_dqbit10/dq";
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit10/fbit2" RLOC = X1Y0;
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit10/fbit2" BEL = "FFY";
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit10/fbit2" U_SET = "ddr1_top0/data_path0/data_read0/ddr1_dqbit10/dq";
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit10/fbit1" RLOC = X3Y0;
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit10/fbit1" BEL = "FFY";
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit10/fbit1" U_SET = "ddr1_top0/data_path0/data_read0/ddr1_dqbit10/dq";
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit10/fbit3" RLOC = X2Y0;
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit10/fbit3" BEL = "FFY";
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit10/fbit3" U_SET = "ddr1_top0/data_path0/data_read0/ddr1_dqbit10/dq";
#############################################################
##  constraints for bit ddr1_dq, 11
INST "ddr1_dq(11)" LOC = N8;
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit11/fbit0" RLOC = X0Y1;
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit11/fbit0" BEL = "FFY";
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit11/fbit0" U_SET = "ddr1_top0/data_path0/data_read0/ddr1_dqbit10/dq";
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit11/fbit2" RLOC = X1Y1;
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit11/fbit2" BEL = "FFY";
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit11/fbit2" U_SET = "ddr1_top0/data_path0/data_read0/ddr1_dqbit10/dq";
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit11/fbit1" RLOC = X3Y1;
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit11/fbit1" BEL = "FFY";
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit11/fbit1" U_SET = "ddr1_top0/data_path0/data_read0/ddr1_dqbit10/dq";
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit11/fbit3" RLOC = X2Y1;
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit11/fbit3" BEL = "FFY";
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit11/fbit3" U_SET = "ddr1_top0/data_path0/data_read0/ddr1_dqbit10/dq";
#############################################################
##  constraints for bit ddr1_dq, 12
INST "ddr1_dq(12)" LOC = N7;
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit12/fbit0" RLOC = X0Y1;
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit12/fbit0" BEL = "FFX";
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit12/fbit0" U_SET = "ddr1_top0/data_path0/data_read0/ddr1_dqbit10/dq";
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit12/fbit2" RLOC = X1Y1;
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit12/fbit2" BEL = "FFX";
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit12/fbit2" U_SET = "ddr1_top0/data_path0/data_read0/ddr1_dqbit10/dq";
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit12/fbit1" RLOC = X3Y1;
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit12/fbit1" BEL = "FFX";
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit12/fbit1" U_SET = "ddr1_top0/data_path0/data_read0/ddr1_dqbit10/dq";
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit12/fbit3" RLOC = X2Y1;
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit12/fbit3" BEL = "FFX";
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit12/fbit3" U_SET = "ddr1_top0/data_path0/data_read0/ddr1_dqbit10/dq";

#############################################################
##  constraints for bit ddr1_dq, 13
INST "ddr1_dq(13)" LOC = L4;
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit13/fbit0" RLOC_ORIGIN = X88Y88;
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit13/fbit0" RLOC = X0Y1;
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit13/fbit0" BEL = "FFY";
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit13/fbit0" U_SET = "ddr1_top0/data_path0/data_read0/ddr1_dqbit13/dq";
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit13/fbit2" RLOC = X1Y1;
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit13/fbit2" BEL = "FFY";
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit13/fbit2" U_SET = "ddr1_top0/data_path0/data_read0/ddr1_dqbit13/dq";
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit13/fbit1" RLOC = X3Y1;
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit13/fbit1" BEL = "FFY";
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit13/fbit1" U_SET = "ddr1_top0/data_path0/data_read0/ddr1_dqbit13/dq";
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit13/fbit3" RLOC = X2Y1;
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit13/fbit3" BEL = "FFY";
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit13/fbit3" U_SET = "ddr1_top0/data_path0/data_read0/ddr1_dqbit13/dq";
#############################################################
##  constraints for bit ddr1_dq, 14
INST "ddr1_dq(14)" LOC = L3;
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit14/fbit0" RLOC = X0Y1;
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit14/fbit0" BEL = "FFX";
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit14/fbit0" U_SET = "ddr1_top0/data_path0/data_read0/ddr1_dqbit13/dq";
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit14/fbit2" RLOC = X1Y1;
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit14/fbit2" BEL = "FFX";
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit14/fbit2" U_SET = "ddr1_top0/data_path0/data_read0/ddr1_dqbit13/dq";
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit14/fbit1" RLOC = X3Y1;
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit14/fbit1" BEL = "FFX";
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit14/fbit1" U_SET = "ddr1_top0/data_path0/data_read0/ddr1_dqbit13/dq";
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit14/fbit3" RLOC = X2Y1;
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit14/fbit3" BEL = "FFX";
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit14/fbit3" U_SET = "ddr1_top0/data_path0/data_read0/ddr1_dqbit13/dq";

#############################################################
##  constraints for bit ddr1_dq, 15
INST "ddr1_dq(15)" LOC = M4;
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit15/fbit0" RLOC_ORIGIN = X88Y86;
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit15/fbit0" RLOC = X0Y0;
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit15/fbit0" BEL = "FFX";
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit15/fbit0" U_SET = "ddr1_top0/data_path0/data_read0/ddr1_dqbit15/dq";
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit15/fbit2" RLOC = X1Y0;
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit15/fbit2" BEL = "FFX";
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit15/fbit2" U_SET = "ddr1_top0/data_path0/data_read0/ddr1_dqbit15/dq";
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit15/fbit1" RLOC = X3Y0;
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit15/fbit1" BEL = "FFX";
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit15/fbit1" U_SET = "ddr1_top0/data_path0/data_read0/ddr1_dqbit15/dq";
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit15/fbit3" RLOC = X2Y0;
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit15/fbit3" BEL = "FFX";
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit15/fbit3" U_SET = "ddr1_top0/data_path0/data_read0/ddr1_dqbit15/dq";
#############################################################