ddr1_test.ucf

xinlinx s vhdl code model and user guider

INST ddr1_top0/data_path0/data_read_controller0/rst_dqs_div_delay0/five LOC = SLICE_X91Y72;
INST ddr1_top0/data_path0/data_read_controller0/rst_dqs_div_delay0/five BEL = G;
INST ddr1_top0/data_path0/data_read_controller0/rst_dqs_div_delay0/six LOC = SLICE_X91Y73;
INST ddr1_top0/data_path0/data_read_controller0/rst_dqs_div_delay0/six BEL = G;

#############################################################
##  constraints for bit ddr1_dqs, 0
INST "ddr1_dqs(0)" LOC = E1;
## LUT location constraints for col 0
INST "ddr1_top0/data_path0/data_read_controller0/dqs_delay0_col0/one" LOC = SLICE_X90Y106;
INST "ddr1_top0/data_path0/data_read_controller0/dqs_delay0_col0/one" BEL = F;
INST "ddr1_top0/data_path0/data_read_controller0/dqs_delay0_col0/two" LOC = SLICE_X90Y107;
INST "ddr1_top0/data_path0/data_read_controller0/dqs_delay0_col0/two" BEL = F;
INST "ddr1_top0/data_path0/data_read_controller0/dqs_delay0_col0/three" LOC = SLICE_X90Y107;
INST "ddr1_top0/data_path0/data_read_controller0/dqs_delay0_col0/three" BEL = G;
INST "ddr1_top0/data_path0/data_read_controller0/dqs_delay0_col0/four" LOC = SLICE_X91Y106;
INST "ddr1_top0/data_path0/data_read_controller0/dqs_delay0_col0/four" BEL = F;
INST "ddr1_top0/data_path0/data_read_controller0/dqs_delay0_col0/five" LOC = SLICE_X91Y106;
INST "ddr1_top0/data_path0/data_read_controller0/dqs_delay0_col0/five" BEL = G;
INST "ddr1_top0/data_path0/data_read_controller0/dqs_delay0_col0/six" LOC = SLICE_X91Y107;
INST "ddr1_top0/data_path0/data_read_controller0/dqs_delay0_col0/six" BEL = G;

## LUT location constraints for col 1
INST "ddr1_top0/data_path0/data_read_controller0/dqs_delay0_col1/one" LOC = SLICE_X88Y106;
INST "ddr1_top0/data_path0/data_read_controller0/dqs_delay0_col1/one" BEL = F;
INST "ddr1_top0/data_path0/data_read_controller0/dqs_delay0_col1/two" LOC = SLICE_X88Y107;
INST "ddr1_top0/data_path0/data_read_controller0/dqs_delay0_col1/two" BEL = F;
INST "ddr1_top0/data_path0/data_read_controller0/dqs_delay0_col1/three" LOC = SLICE_X88Y107;
INST "ddr1_top0/data_path0/data_read_controller0/dqs_delay0_col1/three" BEL = G;
INST "ddr1_top0/data_path0/data_read_controller0/dqs_delay0_col1/four" LOC = SLICE_X89Y106;
INST "ddr1_top0/data_path0/data_read_controller0/dqs_delay0_col1/four" BEL = F;
INST "ddr1_top0/data_path0/data_read_controller0/dqs_delay0_col1/five" LOC = SLICE_X89Y106;
INST "ddr1_top0/data_path0/data_read_controller0/dqs_delay0_col1/five" BEL = G;
INST "ddr1_top0/data_path0/data_read_controller0/dqs_delay0_col1/six" LOC = SLICE_X89Y107;
INST "ddr1_top0/data_path0/data_read_controller0/dqs_delay0_col1/six" BEL = G;
#############################################################
##  constraints for bit ddr1_dq, 0
INST "ddr1_dq(0)" LOC = F5;
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit0/fbit0" RLOC_ORIGIN = X88Y104;
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit0/fbit0" RLOC = X0Y1;
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit0/fbit0" BEL = "FFY";
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit0/fbit0" U_SET = "ddr1_top0/data_path0/data_read0/ddr1_dqbit0/dq";
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit0/fbit2" RLOC = X1Y1;
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit0/fbit2" BEL = "FFY";
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit0/fbit2" U_SET = "ddr1_top0/data_path0/data_read0/ddr1_dqbit0/dq";
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit0/fbit1" RLOC = X3Y1;
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit0/fbit1" BEL = "FFY";
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit0/fbit1" U_SET = "ddr1_top0/data_path0/data_read0/ddr1_dqbit0/dq";
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit0/fbit3" RLOC = X2Y1;
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit0/fbit3" BEL = "FFY";
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit0/fbit3" U_SET = "ddr1_top0/data_path0/data_read0/ddr1_dqbit0/dq";
#############################################################
##  constraints for bit ddr1_dq, 1
INST "ddr1_dq(1)" LOC = F4;
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit1/fbit0" RLOC = X0Y1;
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit1/fbit0" BEL = "FFX";
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit1/fbit0" U_SET = "ddr1_top0/data_path0/data_read0/ddr1_dqbit0/dq";
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit1/fbit2" RLOC = X1Y1;
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit1/fbit2" BEL = "FFX";
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit1/fbit2" U_SET = "ddr1_top0/data_path0/data_read0/ddr1_dqbit0/dq";
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit1/fbit1" RLOC = X3Y1;
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit1/fbit1" BEL = "FFX";
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit1/fbit1" U_SET = "ddr1_top0/data_path0/data_read0/ddr1_dqbit0/dq";
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit1/fbit3" RLOC = X2Y1;
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit1/fbit3" BEL = "FFX";
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit1/fbit3" U_SET = "ddr1_top0/data_path0/data_read0/ddr1_dqbit0/dq";

#############################################################
##  constraints for bit ddr1_dq, 2
INST "ddr1_dq(2)" LOC = H2;
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit2/fbit0" RLOC_ORIGIN = X88Y102;
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit2/fbit0" RLOC = X0Y0;
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit2/fbit0" BEL = "FFX";
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit2/fbit0" U_SET = "ddr1_top0/data_path0/data_read0/ddr1_dqbit2/dq";
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit2/fbit2" RLOC = X1Y0;
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit2/fbit2" BEL = "FFX";
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit2/fbit2" U_SET = "ddr1_top0/data_path0/data_read0/ddr1_dqbit2/dq";
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit2/fbit1" RLOC = X3Y0;
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit2/fbit1" BEL = "FFX";
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit2/fbit1" U_SET = "ddr1_top0/data_path0/data_read0/ddr1_dqbit2/dq";
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit2/fbit3" RLOC = X2Y0;
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit2/fbit3" BEL = "FFX";
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit2/fbit3" U_SET = "ddr1_top0/data_path0/data_read0/ddr1_dqbit2/dq";
#############################################################
##  constraints for bit ddr1_dq, 3
INST "ddr1_dq(3)" LOC = H1;
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit3/fbit0" RLOC = X0Y0;
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit3/fbit0" BEL = "FFY";
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit3/fbit0" U_SET = "ddr1_top0/data_path0/data_read0/ddr1_dqbit2/dq";
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit3/fbit2" RLOC = X1Y0;
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit3/fbit2" BEL = "FFY";
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit3/fbit2" U_SET = "ddr1_top0/data_path0/data_read0/ddr1_dqbit2/dq";
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit3/fbit1" RLOC = X3Y0;
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit3/fbit1" BEL = "FFY";
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit3/fbit1" U_SET = "ddr1_top0/data_path0/data_read0/ddr1_dqbit2/dq";
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit3/fbit3" RLOC = X2Y0;
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit3/fbit3" BEL = "FFY";
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit3/fbit3" U_SET = "ddr1_top0/data_path0/data_read0/ddr1_dqbit2/dq";
#############################################################
##  constraints for bit ddr1_dq, 4
INST "ddr1_dq(4)" LOC = M10;
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit4/fbit0" RLOC = X0Y1;
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit4/fbit0" BEL = "FFY";
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit4/fbit0" U_SET = "ddr1_top0/data_path0/data_read0/ddr1_dqbit2/dq";
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit4/fbit2" RLOC = X1Y1;
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit4/fbit2" BEL = "FFY";
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit4/fbit2" U_SET = "ddr1_top0/data_path0/data_read0/ddr1_dqbit2/dq";
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit4/fbit1" RLOC = X3Y1;
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit4/fbit1" BEL = "FFY";
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit4/fbit1" U_SET = "ddr1_top0/data_path0/data_read0/ddr1_dqbit2/dq";
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit4/fbit3" RLOC = X2Y1;
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit4/fbit3" BEL = "FFY";
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit4/fbit3" U_SET = "ddr1_top0/data_path0/data_read0/ddr1_dqbit2/dq";
#############################################################
##  constraints for bit ddr1_dq, 5
INST "ddr1_dq(5)" LOC = M9;
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit5/fbit0" RLOC = X0Y1;
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit5/fbit0" BEL = "FFX";
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit5/fbit0" U_SET = "ddr1_top0/data_path0/data_read0/ddr1_dqbit2/dq";
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit5/fbit2" RLOC = X1Y1;
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit5/fbit2" BEL = "FFX";
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit5/fbit2" U_SET = "ddr1_top0/data_path0/data_read0/ddr1_dqbit2/dq";
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit5/fbit1" RLOC = X3Y1;
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit5/fbit1" BEL = "FFX";
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit5/fbit1" U_SET = "ddr1_top0/data_path0/data_read0/ddr1_dqbit2/dq";
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit5/fbit3" RLOC = X2Y1;
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit5/fbit3" BEL = "FFX";
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit5/fbit3" U_SET = "ddr1_top0/data_path0/data_read0/ddr1_dqbit2/dq";

#############################################################
##  constraints for bit ddr1_dq, 6
INST "ddr1_dq(6)" LOC = K5;
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit6/fbit0" RLOC_ORIGIN = X88Y100;
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit6/fbit0" RLOC = X0Y1;
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit6/fbit0" BEL = "FFY";
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit6/fbit0" U_SET = "ddr1_top0/data_path0/data_read0/ddr1_dqbit6/dq";
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit6/fbit2" RLOC = X1Y1;
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit6/fbit2" BEL = "FFY";
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit6/fbit2" U_SET = "ddr1_top0/data_path0/data_read0/ddr1_dqbit6/dq";
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit6/fbit1" RLOC = X3Y1;
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit6/fbit1" BEL = "FFY";
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit6/fbit1" U_SET = "ddr1_top0/data_path0/data_read0/ddr1_dqbit6/dq";
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit6/fbit3" RLOC = X2Y1;
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit6/fbit3" BEL = "FFY";
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit6/fbit3" U_SET = "ddr1_top0/data_path0/data_read0/ddr1_dqbit6/dq";
#############################################################
##  constraints for bit ddr1_dq, 7
INST "ddr1_dq(7)" LOC = K4;
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit7/fbit0" RLOC = X0Y1;
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit7/fbit0" BEL = "FFX";
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit7/fbit0" U_SET = "ddr1_top0/data_path0/data_read0/ddr1_dqbit6/dq";
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit7/fbit2" RLOC = X1Y1;
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit7/fbit2" BEL = "FFX";
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit7/fbit2" U_SET = "ddr1_top0/data_path0/data_read0/ddr1_dqbit6/dq";
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit7/fbit1" RLOC = X3Y1;
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit7/fbit1" BEL = "FFX";
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit7/fbit1" U_SET = "ddr1_top0/data_path0/data_read0/ddr1_dqbit6/dq";
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit7/fbit3" RLOC = X2Y1;
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit7/fbit3" BEL = "FFX";
INST "ddr1_top0/data_path0/data_read0/ddr1_dqbit7/fbit3" U_SET = "ddr1_top0/data_path0/data_read0/ddr1_dqbit6/dq";

#############################################################
##  constraints for bit no_dpin, 0
INST "ddr1_top0/data_path0/data_read_controller0/ddr1_dqs_div0/col0" LOC = SLICE_X91Y99;
INST "ddr1_top0/data_path0/data_read_controller0/ddr1_dqs_div0/col1" LOC = SLICE_X89Y99;
NET "ddr1_top0/data_path0/data_read_controller0/ddr1_dqs_div0/dqs_divn" MAXDELAY = 1200ps;
NET "ddr1_top0/data_path0/data_read_controller0/ddr1_dqs_div0/dqs_divp" MAXDELAY = 1200ps;
INST "ddr1_top0/data_path0/data_read_controller0/ddr1_transfer_done0/xdone0_clk0" LOC = SLICE_X89Y98;
INST "ddr1_top0/data_path0/data_read_controller0/ddr1_transfer_done0/xdone0_clk0" BEL = FFX;
INST "ddr1_top0/data_path0/data_read_controller0/ddr1_transfer_done0/xdone0_clk90" LOC = SLICE_X91Y98;
INST "ddr1_top0/data_path0/data_read_controller0/ddr1_transfer_done0/xdone0_clk90" BEL = FFX;
INST "ddr1_top0/data_path0/data_read_controller0/ddr1_transfer_done0/xdone0_rst90" LOC = SLICE_X91Y98;
INST "ddr1_top0/data_path0/data_read_controller0/ddr1_transfer_done0/xdone0_rst90" BEL = G;
INST "ddr1_top0/data_path0/data_read_controller0/ddr1_transfer_done0/xdone0_clk180" LOC = SLICE_X88Y99;
INST "ddr1_top0/data_path0/data_read_controller0/ddr1_transfer_done0/xdone0_clk180" BEL = FFX;
INST "ddr1_top0/data_path0/data_read_controller0/ddr1_transfer_done0/xdone0_clk270" LOC = SLICE_X90Y99;
INST "ddr1_top0/data_path0/data_read_controller0/ddr1_transfer_done0/xdone0_clk270" BEL = FFX;
INST "ddr1_top0/data_path0/data_read_controller0/ddr1_transfer_done0/xdone0_rst270" LOC = SLICE_X90Y99;
INST "ddr1_top0/data_path0/data_read_controller0/ddr1_transfer_done0/xdone0_rst270" BEL = G;