📄 ddr1_test.ucf
字号:
############################################################################
##
## Xilinx, Inc. 2004 www.xilinx.com
## Thu October 14 7:54:35 2004
##
##
############################################################################
## File name : ddr1_test.ucf
##
## Description : Constraints file
## targetted to xc2vp20-6 ff1152
##
############################################################################
############################################################################
# Clock constraints #
############################################################################
NET "ddr1_top0/iobs0/sys_clk_ibuf" TNM_NET = FFS(*) "SYS_CLK";
TIMESPEC "TS_SYS_CLK" = PERIOD "SYS_CLK" 5.000000 ns HIGH 50 %;
############################################################################
# I/O STANDARDS #
############################################################################
# SSTL2_II for input or output signals
NET "SYS_CLK*" IOSTANDARD = LVDS_25;
NET "ddr1_dq(*)" IOSTANDARD = SSTL2_II;
NET "ddr1_dqs(*)" IOSTANDARD = SSTL2_II;
NET "ddr1_dm(*)" IOSTANDARD = SSTL2_II;
NET "ddr1_clk*" IOSTANDARD = SSTL2_II;
NET "ddr1_clk*b" IOSTANDARD = SSTL2_II;
NET "ddr1_address(*)" IOSTANDARD = SSTL2_II;
NET "ddr1_ba(*)" IOSTANDARD = SSTL2_II;
NET "ddr1_rasb" IOSTANDARD = SSTL2_II;
NET "ddr1_casb" IOSTANDARD = SSTL2_II;
NET "ddr1_web" IOSTANDARD = SSTL2_II;
NET "ddr1_csb" IOSTANDARD = SSTL2_II;
NET "ddr1_cke" IOSTANDARD = SSTL2_II;
NET "reset_in" IOSTANDARD = LVCMOS25;
NET "led_error_output1" IOSTANDARD = LVCMOS25;
NET "dip1" IOSTANDARD = LVCMOS25;
############################################################################
# IO Signals Registering Constraints #
############################################################################
INST "ddr1_top0/controller0/ddr_address*" IOB = TRUE;
INST "ddr1_top0/controller0/ddr_ba*" IOB = TRUE;
INST "ddr1_top0/iobs0/controller_iobs0/iob_rasb" IOB = TRUE;
INST "ddr1_top0/iobs0/controller_iobs0/iob_casb" IOB = TRUE;
INST "ddr1_top0/iobs0/controller_iobs0/iob_web" IOB = TRUE;
#############################################################################
# Calibration Circuit Constraints #
#############################################################################
NET "ddr1_top0/infrastructure0/cal_top0/seltap(4)" S;
NET "ddr1_top0/infrastructure0/cal_top0/ckt_to_cal/delay1" KEEP;
NET "ddr1_top0/infrastructure0/cal_top0/ckt_to_cal/delay2" KEEP;
NET "ddr1_top0/infrastructure0/cal_top0/ckt_to_cal/delay3" KEEP;
NET "ddr1_top0/infrastructure0/cal_top0/ckt_to_cal/delay4" KEEP;
NET "ddr1_top0/infrastructure0/cal_top0/ckt_to_cal/delay5" KEEP;
##############################################################################
# MaxDelay constraints #
##############################################################################
############################################################################
# Banks 23
# Pin Location Constraints for Clock, Address, and Controls
############################################################################
INST "SYS_CLKb" LOC = "E18";
INST "SYS_CLK" LOC = "D18";
NET "ddr1_clk0" LOC = "F7" ;
NET "ddr1_clk0b" LOC = "F8" ;
NET "ddr1_clk1" LOC = "E3" ;
NET "ddr1_clk1b" LOC = "E4" ;
NET "ddr1_clk2" LOC = "J7" ;
NET "ddr1_clk2b" LOC = "J8" ;
NET "ddr1_clk3" LOC = "L7" ;
NET "ddr1_clk3b" LOC = "L8" ;
NET "ddr1_clk4" LOC = "L5" ;
NET "ddr1_clk4b" LOC = "L6" ;
NET "ddr1_dm(0)" LOC = "N9" ;
NET "ddr1_dm(1)" LOC = "N10" ;
NET "ddr1_dm(2)" LOC = "P9" ;
NET "ddr1_dm(3)" LOC = "P10" ;
NET "ddr1_dm(4)" LOC = "N5" ;
NET "ddr1_dm(5)" LOC = "N6" ;
NET "ddr1_dm(6)" LOC = "P7" ;
NET "ddr1_dm(7)" LOC = "P8" ;
NET "ddr1_dm(8)" LOC = "U11" ;
NET "ddr1_cke" LOC = "T9" ;
NET "ddr1_csb" LOC = "U9" ;
NET "ddr1_rasb" LOC = "U5" ;
NET "ddr1_casb" LOC = "U7" ;
NET "ddr1_web" LOC = "W4" ;
NET "ddr1_ba(0)" LOC = "Y7" ;
NET "ddr1_ba(1)" LOC = "AB2" ;
NET "ddr1_address(12)" LOC = "AA4" ;
NET "ddr1_address(11)" LOC = "AB6" ;
NET "ddr1_address(10)" LOC = "AC4" ;
NET "ddr1_address(9)" LOC = "AD6" ;
NET "ddr1_address(8)" LOC = "AF2" ;
NET "ddr1_address(7)" LOC = "AE5" ;
NET "ddr1_address(6)" LOC = "AH6" ;
NET "ddr1_address(5)" LOC = "AJ8" ;
NET "ddr1_address(4)" LOC = "T10" ;
NET "ddr1_address(3)" LOC = "U10" ;
NET "ddr1_address(2)" LOC = "U6" ;
NET "ddr1_address(1)" LOC = "U8" ;
NET "ddr1_address(0)" LOC = "W3" ;
NET "reset_in" LOC = "Y6" ;
NET "led_error_output1" LOC = "AA2" ;
NET "dip1" LOC = "AA3" ;
#########################################################################
# MAXDELAY constraints #
#########################################################################
NET "ddr1_top0/data_path0/data_read0/fbit_0(*)" MAXDELAY = 1200ps;
NET "ddr1_top0/data_path0/data_read0/fbit_1(*)" MAXDELAY = 1200ps;
NET "ddr1_top0/data_path0/data_read0/fbit_2(*)" MAXDELAY = 1200ps;
NET "ddr1_top0/data_path0/data_read0/fbit_3(*)" MAXDELAY = 1200ps;
NET "ddr1_top0/controller0/rst_dqs_div_int" MAXDELAY = 600ps ;
NET "ddr1_top0/data_path0/data_read_controller0/rst_dqs_div_delayed" MAXDELAY = 1500ps;
NET "ddr1_top0/data_path0/data_read_controller0/fifo_*_wr_addr*" MAXDELAY = 3000ps;
NET "ddr1_top0/data_path0/data_read0/fifo_*_rd_addr*" MAXDELAY = 3000ps;
NET "ddr1_top0/data_path0/data_read_controller0/transfer_done_*" MAXDELAY = 1500ps;
#########################################################################
############################################################################
# DCM, MACRO and BUFG Constraints
############################################################################
INST "ddr1_top0/infrastructure0/clk_dcm0/DCM_INST1" LOC="DCM_X3Y1";
INST "ddr1_top0/infrastructure0/clk_dcm0/BUFG_CLK0/u1" LOC="BUFGMUX6S";
INST "ddr1_top0/infrastructure0/clk_dcm0/BUFG_CLK90/u1" LOC="BUFGMUX7P";
NET "ddr1_top0/infrastructure0/cal_top0/clkdiv2" MAXDELAY = 600 ps;
NET "ddr1_top0/infrastructure0/cal_top0/phclkdiv2" MAXDELAY = 600 ps;
NET "ddr1_top0/infrastructure0/cal_top0/suclkdiv2" MAXDELAY = 600ps;
NET "ddr1_top0/infrastructure0/cal_top0/suphclkdiv2" MAXDELAY = 700ps;
############################################################################
# Calibration Circuit Constraints
############################################################################
INST "ddr1_top0/infrastructure0/cal_top0/cal_dcm" LOC="DCM_X2Y1";
INST "ddr1_top0/infrastructure0/cal_top0" AREA_GROUP=gp1;
AREA_GROUP "gp1" RANGE = SLICE_X52Y0:SLICE_X75Y11;
INST "ddr1_top0/infrastructure0/cal_top0/cal_clkd2" LOC = SLICE_X72Y0;
INST "ddr1_top0/infrastructure0/cal_top0/cal_phClkd2" LOC = SLICE_X72Y3;
INST "ddr1_top0/infrastructure0/cal_top0/hxSampReg0" LOC = SLICE_X74Y0;
INST "ddr1_top0/infrastructure0/cal_top0/cal_suClkd2" LOC = SLICE_X72Y4;
INST "ddr1_top0/infrastructure0/cal_top0/cal_suPhClkd2" LOC = SLICE_X74Y5;
INST "ddr1_top0/infrastructure0/cal_top0/phSampReg0" LOC = SLICE_X74Y4;
########################################################################
INST "rst_dqs_div_in" LOC = "R7";
INST "rst_dqs_div_out" LOC = "R6";
INST ddr1_top0/data_path0/data_read_controller0/rst_dqs_div_delay0/one LOC = SLICE_X90Y72;
INST ddr1_top0/data_path0/data_read_controller0/rst_dqs_div_delay0/one BEL = F;
INST ddr1_top0/data_path0/data_read_controller0/rst_dqs_div_delay0/two LOC = SLICE_X90Y73;
INST ddr1_top0/data_path0/data_read_controller0/rst_dqs_div_delay0/two BEL = F;
INST ddr1_top0/data_path0/data_read_controller0/rst_dqs_div_delay0/three LOC = SLICE_X90Y73;
INST ddr1_top0/data_path0/data_read_controller0/rst_dqs_div_delay0/three BEL = G;
INST ddr1_top0/data_path0/data_read_controller0/rst_dqs_div_delay0/four LOC = SLICE_X91Y72;
INST ddr1_top0/data_path0/data_read_controller0/rst_dqs_div_delay0/four BEL = F;
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -