ddr1_test.sdc

xinlinx s vhdl code model and user guider

# generic/phy_data

define_global_attribute          xc_global_buffers {2}
define_attribute          {ddr1_top0.data_path0.data_read_controller0.dqs_delay0_col0} syn_noclockbuf {1}
define_attribute          {ddr1_top0.data_path0.data_read_controller0.dqs_delay0_col1} syn_noclockbuf {1}
define_attribute          {ddr1_top0.data_path0.data_read_controller0.dqs_delay1_col0} syn_noclockbuf {1}
define_attribute          {ddr1_top0.data_path0.data_read_controller0.dqs_delay1_col1} syn_noclockbuf {1}
define_attribute          {ddr1_top0.data_path0.data_read_controller0.dqs_delay2_col0} syn_noclockbuf {1}
define_attribute          {ddr1_top0.data_path0.data_read_controller0.dqs_delay2_col1} syn_noclockbuf {1}
define_attribute          {ddr1_top0.data_path0.data_read_controller0.dqs_delay3_col0} syn_noclockbuf {1}
define_attribute          {ddr1_top0.data_path0.data_read_controller0.dqs_delay3_col1} syn_noclockbuf {1}
define_attribute          {ddr1_top0.data_path0.data_read_controller0.dqs_delay4_col0} syn_noclockbuf {1}
define_attribute          {ddr1_top0.data_path0.data_read_controller0.dqs_delay4_col1} syn_noclockbuf {1}
define_attribute          {ddr1_top0.data_path0.data_read_controller0.dqs_delay5_col0} syn_noclockbuf {1}
define_attribute          {ddr1_top0.data_path0.data_read_controller0.dqs_delay5_col1} syn_noclockbuf {1}
define_attribute          {ddr1_top0.data_path0.data_read_controller0.dqs_delay6_col0} syn_noclockbuf {1}
define_attribute          {ddr1_top0.data_path0.data_read_controller0.dqs_delay6_col1} syn_noclockbuf {1}
define_attribute          {ddr1_top0.data_path0.data_read_controller0.dqs_delay7_col0} syn_noclockbuf {1}
define_attribute          {ddr1_top0.data_path0.data_read_controller0.dqs_delay7_col1} syn_noclockbuf {1}
define_attribute          {ddr1_top0.data_path0.data_read_controller0.dqs_delay8_col0} syn_noclockbuf {1}
define_attribute          {ddr1_top0.data_path0.data_read_controller0.dqs_delay8_col1} syn_noclockbuf {1}
define_attribute          {ddr1_top0.data_path0.data_read_controller0.dqs_delay9_col0} syn_noclockbuf {1}
define_attribute          {ddr1_top0.data_path0.data_read_controller0.dqs_delay9_col1} syn_noclockbuf {1}
define_attribute          {ddr1_top0.data_path0.data_read_controller0.dqs_delay10_col0} syn_noclockbuf {1}
define_attribute          {ddr1_top0.data_path0.data_read_controller0.dqs_delay10_col1} syn_noclockbuf {1}
define_attribute          {ddr1_top0.data_path0.data_read_controller0.dqs_delay11_col0} syn_noclockbuf {1}
define_attribute          {ddr1_top0.data_path0.data_read_controller0.dqs_delay11_col1} syn_noclockbuf {1}
define_attribute          {ddr1_top0.data_path0.data_read_controller0.dqs_delay12_col0} syn_noclockbuf {1}
define_attribute          {ddr1_top0.data_path0.data_read_controller0.dqs_delay12_col1} syn_noclockbuf {1}
define_attribute          {ddr1_top0.data_path0.data_read_controller0.dqs_delay13_col0} syn_noclockbuf {1}
define_attribute          {ddr1_top0.data_path0.data_read_controller0.dqs_delay13_col1} syn_noclockbuf {1}
define_attribute          {ddr1_top0.data_path0.data_read_controller0.dqs_delay14_col0} syn_noclockbuf {1}
define_attribute          {ddr1_top0.data_path0.data_read_controller0.dqs_delay14_col1} syn_noclockbuf {1}
define_attribute          {ddr1_top0.data_path0.data_read_controller0.dqs_delay15_col0} syn_noclockbuf {1}
define_attribute          {ddr1_top0.data_path0.data_read_controller0.dqs_delay15_col1} syn_noclockbuf {1}
define_attribute          {ddr1_top0.data_path0.data_read_controller0.dqs_delay16_col0} syn_noclockbuf {1}
define_attribute          {ddr1_top0.data_path0.data_read_controller0.dqs_delay16_col1} syn_noclockbuf {1}
define_attribute          {ddr1_top0.data_path0.data_read_controller0.dqs_delay17_col0} syn_noclockbuf {1}
define_attribute          {ddr1_top0.data_path0.data_read_controller0.dqs_delay17_col1} syn_noclockbuf {1}

define_global_attribute          syn_replicate {0}
define_attribute          {v:work.cal_ctl} syn_hier {hard}
define_attribute          {v:work.cal_div2} syn_hier {hard}
define_attribute          {v:work.cal_reg} syn_hier {hard}
define_attribute          {v:work.cal_top} syn_hier {hard}
define_attribute          {v:work.clk_dcm} syn_hier {hard}
define_attribute          {v:work.data_path} syn_hier {hard}
define_attribute          {v:work.data_path_iobs} syn_hier {hard}
define_attribute          {v:work.data_path_rst} syn_hier {hard}
define_attribute          {v:work.data_read} syn_hier {hard}
define_attribute          {v:work.data_read_controller} syn_hier {hard}
define_attribute          {v:work.data_write} syn_hier {hard}
define_attribute          {v:work.ddr1_dm} syn_hier {hard}
define_attribute          {v:work.ddr1_dqbit} syn_hier {hard}
define_attribute          {v:work.ddr1_dqs_div} syn_hier {hard}
define_attribute          {v:work.ddr1_top} syn_hier {hard}
define_attribute          {v:work.ddr1_transfer_done} syn_hier {hard}
define_attribute          {v:work.dqs_delay} syn_hier {hard}
define_attribute          {v:work.infrastructure} syn_hier {hard}
define_attribute          {v:work.infrastructure_iobs} syn_hier {hard}
define_attribute          {v:work.iobs} syn_hier {hard}
define_attribute          {v:work.LUT2} syn_hier {hard}
define_attribute          {v:work.LUT3} syn_hier {hard}
define_attribute          {v:work.LUT4Z0} syn_hier {hard}
define_attribute          {v:work.LUT4Z1} syn_hier {hard}
define_attribute          {v:work.LUT4Z2} syn_hier {hard}
define_attribute          {v:work.LUT4Z3} syn_hier {hard}
define_attribute          {v:work.mybufg} syn_hier {hard}
define_attribute          {v:work.RAM_8D} syn_hier {hard}
define_attribute          {v:work.ddr_dq_iob} syn_hier {hard}
define_attribute          {v:work.ddr_dqs_iob} syn_hier {hard}
define_global_attribute          syn_edif_bit_format {%n(%i)}

#####phy1_xmil007_rel2

define_attribute          {v:work.controller_iobs} syn_hier {hard}
#####phy2_xmil007_rel2

define_attribute          {v:work.addr_gen} syn_hier {hard}
define_attribute          {v:work.cmd_fsm} syn_hier {hard}
define_attribute          {v:work.cmp_data} syn_hier {hard}
define_attribute          {v:work.controller} syn_hier {hard}
define_attribute          {v:work.ddr1_test} syn_hier {hard}
define_attribute          {v:work.ddr1_test_bench} syn_hier {hard}
define_attribute          {v:work.lfsr32} syn_hier {hard}
define_attribute          {v:work.r_w_dly} syn_hier {hard}
######phy_xmil007_rel2