addr_gen.vhd

xinlinx s vhdl code model and user guider

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
--
-- pragma translate_off
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
-- pragma translate_on
--

entity addr_gen is
port(
   clk            : in std_logic;
   rst            : in std_logic;
   addr_rst       : in std_logic;
   addr_inc       : in std_logic;
   addr_out       : out std_logic_vector(23 downto 0);
   column_address : out std_logic_vector(7 downto 0); 
   test_cnt_ena   : in std_logic;
   test_out       : out std_logic_vector(4 downto 0);
   burst_done     : out std_logic;
   cnt_roll       : out std_logic);
end addr_gen;


architecture arc_addr_gen of addr_gen is

signal addr_reg 			: std_logic_vector(22 downto 0); 
signal addr_int 			: std_logic_vector(22 downto 0);
signal test_cnt 			: std_logic_vector(4 downto 0);
signal testcnt_reg 		: std_logic_vector(3 downto 0);
signal column_counter 	: std_logic_vector(7 downto 0);
signal row_counter    	: std_logic_vector(7 downto 0);
signal ba_count       	: std_logic_vector(1 downto 0);
signal cnt            	: std_logic_vector(1 downto 0);
signal burst_done_reg   : std_logic;
signal burst_done_1_reg : std_logic;
signal cnt_roll_p     	: std_logic;
signal cnt_roll_p2    	:std_logic;

begin

ba_count       <= "00"; 
column_address <= column_counter;
addr_out <= "00000000000100" & column_counter & ba_count;
burst_done <=     burst_done_1_reg;

process(clk)
begin
  if clk'event and clk = '1' then
     if (rst = '1' or addr_rst = '1') then
        column_counter <= "00000000";
        row_counter    <= "00000000";
        cnt <= "00";
      elsif addr_inc = '1' then
       
       		if cnt = "01" then 
            			cnt <= "00";
        		else
            			cnt <= cnt + "01";
        		end if;
        
        		if test_cnt_ena = '1' and cnt = "01" then 
        
          			 if column_counter = "11110000" then  --11110000
        
                 				column_counter <= "00000000";
           			else 
                				column_counter <= column_counter + "00000100";
            			end if;     
          		else 
             			column_counter <= column_counter;
        		end if;
        
     end if;
    end if;
end process;




process(clk)
begin
  if clk'event and clk = '1' then
  if rst = '1' then
     burst_done_reg <= '0';
     burst_done_1_reg <= '0';
  elsif (column_counter = "11101100" ) then   --burst length =4   --11101100
     burst_done_reg <= '1';
     
  else
     burst_done_reg <= '0';
  end if;
      burst_done_1_reg <= burst_done_reg;
 end if;
end process;



process(clk)
begin
 if clk'event and clk = '1' then
  if rst = '1' then
     cnt_roll_p <= '0';
    elsif (column_counter = "11101100" ) then  --burst length =4 
     cnt_roll_p <= '1';
  else
     cnt_roll_p <= '0';
  end if;
 end if;
end process;

process(clk)
begin
 if clk'event and clk = '1' then
  if rst = '1' then
     cnt_roll_p2 <= '0';
     cnt_roll    <= '0';
  else
     cnt_roll_p2  <= cnt_roll_p;
     cnt_roll <= cnt_roll_p2;
  end if;
 end if;
end process;




--  TO TEST SINGLE BUSRT 

--process (clk)
--begin
-- if clk'event and clk = '1' then
--  if rst = '1' then
--     cnt_roll_p <= '0';
--  elsif(addr_inc = '1') then
--       cnt_roll <= '1';
--  else
--      cnt_roll <= '0';
--  end if;
--  end if;    
--end process;

--process (clk)
--begin
-- if clk'event and clk = '1' then
--  if rst = '1' then
--     burst_done_reg   <= '0';
--     burst_done_1_reg <= '0';
--     column_counter <= "00000100";
--   elsif (addr_inc = '1') then
--     burst_done_reg <= '1';
--     burst_done_1_reg <= burst_done_reg;
--  else
--     burst_done_reg <= '0';
--     burst_done_1_reg <= burst_done_reg;
-- end if;
-- end if;
--end process;




end arc_addr_gen;