📄 ddr1_test.vhd
字号:
library IEEE;
use IEEE.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
--library synplify;
--use synplify.attributes.all;
--
-- pragma translate_off
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
-- pragma translate_on
--
entity ddr1_test is
port(
dip1 : in STD_LOGIC;
dip2 : in std_logic;
dip3 : in std_logic;
reset_in : in STD_LOGIC;
SYS_CLK : in STD_LOGIC;
SYS_CLKb : in std_logic;
rst_dqs_div_in : in std_logic;
rst_dqs_div_out : out std_logic;
ddr1_casb : out STD_LOGIC;
ddr1_cke : out STD_LOGIC;
ddr1_clk0 : out STD_LOGIC;
ddr1_clk0b : out STD_LOGIC;
ddr1_clk1 : out STD_LOGIC;
ddr1_clk1b : out STD_LOGIC;
ddr1_clk2 : out STD_LOGIC;
ddr1_clk2b : out STD_LOGIC;
ddr1_clk3 : out STD_LOGIC;
ddr1_clk3b : out STD_LOGIC;
ddr1_clk4 : out STD_LOGIC;
ddr1_clk4b : out STD_LOGIC;
ddr1_csb : out STD_LOGIC;
ddr1_rasb : out STD_LOGIC;
ddr1_web : out STD_LOGIC;
ddr1_address : out STD_LOGIC_VECTOR(12 downto 0);
ddr1_ba : out STD_LOGIC_VECTOR(1 downto 0);
ddr1_dm : out STD_LOGIC_VECTOR(8 downto 0);
led_error_output1 : out std_logic;
ddr1_dq : inout STD_LOGIC_VECTOR(71 downto 0);
ddr1_dqs : inout STD_LOGIC_VECTOR(8 downto 0)
);
end ddr1_test;
architecture arc_ddr1_test of ddr1_test is
---- Component declarations -----
component ddr1_test_bench
port(
dip2 : in std_logic;
fpga_clk : in std_logic;
fpga_rst90 : in std_logic;
fpga_rst0 : in std_logic;
fpga_rst180 : in std_logic;
fpga_rst270 : in std_logic;
clk90 : in std_logic;
burst_done : out std_logic;
INIT_DONE : in std_logic;
ar_done : in std_logic;
u_ack : in std_logic;
u_data_val : in std_logic;
u_data_o : in std_logic_vector(143 downto 0);
u_addr : out std_logic_vector(23 downto 0);
u_cmd : out std_logic_vector(2 downto 0);
u_data_i : out std_logic_vector(143 downto 0);
u_config_parms : out std_logic_vector(9 downto 0);
led_error_output : out std_logic;
data_valid_out : out std_logic
);
end component;
component ddr1_top
port(
SYS_CLK : in std_logic;
SYS_CLKb : in std_logic;
dip1 : in std_logic;
rst_dqs_div_in : in std_logic;
rst_dqs_div_out : out std_logic;
reset_in : in std_logic;
user_input_data : in std_logic_vector(143 downto 0);
user_output_data : out std_logic_vector(143 downto 0):=(OTHERS => 'Z');
user_data_valid : out std_logic;
user_input_address : in std_logic_vector(21 downto 0);
user_bank_address : in std_logic_vector(1 downto 0);
user_config_register : in std_logic_vector(9 downto 0);
user_command_register : in std_logic_vector(2 downto 0);
user_cmd_ack : out std_logic;
burst_done : in std_logic;
init_val : out std_logic;
ar_done : out std_logic;
ddr_dqs : inout std_logic_vector(8 downto 0);
ddr_dq : inout std_logic_vector(71 downto 0):= (OTHERS => 'Z');
ddr_cke : out std_logic;
ddr_csb : out std_logic;
ddr_rasb : out std_logic;
ddr_casb : out std_logic;
ddr_web : out std_logic;
ddr_dm : out std_logic_vector(8 downto 0);
ddr_ba : out std_logic_vector(1 downto 0);
ddr_address : out std_logic_vector(12 downto 0);
ddr1_clk0 : out std_logic;
ddr1_clk0b : out std_logic;
ddr1_clk1 : out std_logic;
ddr1_clk1b : out std_logic;
ddr1_clk2 : out std_logic;
ddr1_clk2b : out std_logic;
ddr1_clk3 : out std_logic;
ddr1_clk3b : out std_logic;
ddr1_clk4 : out std_logic;
ddr1_clk4b : out std_logic;
clk_int_val : out std_logic;
clk90_int_val : out std_logic;
sys_rst_val : out std_logic;
sys_rst90_val : out std_logic;
sys_rst180_val : out std_logic;
sys_rst270_val : out std_logic
);
end component;
---- Signal declarations used on the diagram ----
signal controller1_data_output : std_logic_vector(143 downto 0);
signal u1_address : std_logic_vector(23 downto 0);
signal user_data_val1 : std_logic;
signal u1_config_parms : std_logic_vector(9 downto 0);
signal user_cmd1 : std_logic_vector(2 downto 0);
signal user_ack1 : std_logic;
signal u1_data_i : std_logic_vector(143 downto 0);
signal burst_done_val1 : std_logic;
signal init_val1 : std_logic;
signal pass_val1 : std_logic;
signal ar_done_val1 : std_logic;
signal clk_int : std_logic;
signal clk90_int : std_logic;
signal sys_rst : std_logic;
signal sys_rst90 : std_logic;
signal sys_rst180 : std_logic;
signal sys_rst270 : std_logic;
signal data_valid_out1 : std_logic;
begin
---- Component instantiations ----
ddr1_top0 : ddr1_top port map(
SYS_CLK => SYS_CLK,
SYS_CLKb => SYS_CLKb,
dip1 => dip1,
rst_dqs_div_in => rst_dqs_div_in,
rst_dqs_div_out => rst_dqs_div_out,
reset_in => reset_in,
user_input_data => u1_data_i,
user_output_data => controller1_data_output,
user_data_valid => user_data_val1,
user_input_address => u1_address(23 downto 2),
user_bank_address => u1_address(1 downto 0),
user_config_register => u1_config_parms,
user_command_register => user_cmd1,
user_cmd_ack => user_ack1,
burst_done => burst_done_val1,
init_val => init_val1,
ar_done => ar_done_val1,
ddr_dqs => ddr1_dqs,
ddr_dq => ddr1_dq,
ddr_cke => ddr1_cke,
ddr_csb => ddr1_csb,
ddr_rasb => ddr1_rasb,
ddr_casb => ddr1_casb,
ddr_web => ddr1_web,
ddr_dm => ddr1_dm,
ddr_ba => ddr1_ba,
ddr_address => ddr1_address,
ddr1_clk0 => ddr1_clk0,
ddr1_clk0b => ddr1_clk0b,
ddr1_clk1 => ddr1_clk1,
ddr1_clk1b => ddr1_clk1b,
ddr1_clk2 => ddr1_clk2,
ddr1_clk2b => ddr1_clk2b,
ddr1_clk3 => ddr1_clk3,
ddr1_clk3b => ddr1_clk3b,
ddr1_clk4 => ddr1_clk4,
ddr1_clk4b => ddr1_clk4b,
clk_int_val => clk_int,
clk90_int_val => clk90_int,
sys_rst_val => sys_rst,
sys_rst90_val => sys_rst90,
sys_rst180_val => sys_rst180,
sys_rst270_val => sys_rst270
);
ddr1_test_bench0 : ddr1_test_bench port map (
dip2 => dip1 ,
fpga_clk => clk_int,
fpga_rst90 => sys_rst90,
fpga_rst0 => sys_rst,
fpga_rst180 => sys_rst180,
fpga_rst270 => sys_rst270,
clk90 => clk90_int,
burst_done => burst_done_val1,
INIT_DONE => init_val1,
ar_done => ar_done_val1,
u_ack => user_ack1,
u_data_val => user_data_val1,
u_data_o => controller1_data_output,
u_addr => u1_address,
u_cmd => user_cmd1,
u_data_i => u1_data_i ,
u_config_parms => u1_config_parms,
led_error_output => led_error_output1,
data_valid_out => data_valid_out1
);
end arc_ddr1_test;
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -