ddr1_test_bench.vhd

xinlinx s vhdl code model and user guider

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity ddr1_test_bench is
port(
     dip2           : in std_logic;
     fpga_clk       : in std_logic;
     fpga_rst90     : in std_logic;
     fpga_rst0      : in std_logic;
     fpga_rst180    : in std_logic;
     fpga_rst270    : in std_logic;     
     clk90          : in std_logic;
     burst_done     : out std_logic;
     INIT_DONE      : in std_logic;
     ar_done        : in std_logic;
     u_ack          : in std_logic;
     u_data_val     : in std_logic;
     u_data_o       : in std_logic_vector(143 downto 0);
     u_addr         : out std_logic_vector(23 downto 0);
     u_cmd          : out std_logic_vector(2 downto 0);
     u_data_i       : out std_logic_vector(143 downto 0);
     u_config_parms : out std_logic_vector(9 downto 0);
     led_error_output : out std_logic;
     data_valid_out : out std_logic     
     );
end ddr1_test_bench;

 
architecture arc_ddr1_test_bench of ddr1_test_bench is

component addr_gen
port(
     clk            : in std_logic;
     rst            : in std_logic;
     addr_rst       : in std_logic;
     addr_inc       : in std_logic;
     addr_out       : out std_logic_vector(23 downto 0);
     column_address : out std_logic_vector(7 downto 0); 
     test_cnt_ena   : in std_logic;
     test_out       : out std_logic_vector(4 downto 0);
     burst_done     : out std_logic;
     cnt_roll       : out std_logic
     );
end component;

component cmd_fsm 
port (
      clk          : in std_logic;
      clk90        : in std_logic;
      cmd_ack      : in std_logic;
      cnt_roll     : in std_logic;
      dip2         : in std_logic;
      dly_tc       : in std_logic;
      r_w          : in std_logic;
      refresh_done : in std_logic;
      rst          : in std_logic;
      rst90        : in std_logic;
      rst180       : in std_logic;
      init_val     : in std_logic;
      u_data_val   : in std_logic;
      addr_inc     : out std_logic;
      addr_rst     : out std_logic;
      u_cmd        : out std_logic_vector(2 downto 0);
      dly_inc      : out std_logic;
      init_counter : out std_logic_vector(6 downto 0);
      lfsr_rst     : out std_logic);     
end component;

component cmp_data
port(
     clk            : in std_logic;
     data_valid     : in std_logic;
     lfsr_data      : in std_logic_vector(143 downto 0);
     read_data      : in std_logic_vector(143 downto 0);
     rst            : in std_logic;
     led_error_output : out std_logic;
     data_valid_out : out std_logic
     );
end component;  

component r_w_dly
port(
      clk     : in std_logic;
      rst     : in std_logic;
      dly_inc : in std_logic;
      dly_tc  : out std_logic;
      r_w     : out std_logic
      );
end component;

component lfsr32
port (
        clk      : in std_logic;
        rst      : in std_logic;
        lfsr_rst : in std_logic;
        lfsr_ena : in std_logic;
        lfsr_out : out std_logic_vector(143 downto 0)
        );
end component;


signal clk                  : std_logic;
signal rst0_r               : std_logic;
signal rst90_r              : std_logic;
signal rst180_r             : std_logic;
signal rst270_r             : std_logic;
signal user_data_val        : std_logic;
signal addr_inc             : std_logic;
signal addr_rst             : std_logic;
signal cmd_ack              : std_logic;
signal cnt_roll             : std_logic;
signal ctrl_ready           : std_logic;
signal data_valid           : std_logic;
signal dly_inc              : std_logic;
signal dly_tc               : std_logic;
signal lfsr_ena             : std_logic;
signal lfsr_rst             : std_logic;
signal r_w                  : std_logic;
signal addr                 : std_logic_vector(22 downto 0);
signal cmd                  : std_logic_vector(6 downto 0);
signal lfsr_data            : std_logic_vector(143 downto 0);
signal test_cnt             : std_logic_vector(4 downto 0);
signal udi                  : std_logic_vector(15 downto 0);
signal u_n_x                : std_logic_vector(3 downto 0);
signal addr_out             : std_logic_vector(23 downto 0);
signal pass_val             : std_logic;
signal state                : std_logic_vector(6 downto 0);
signal column_address_count : std_logic_vector(7 downto 0); 
--signal lfsr_ena_read		: std_logic;
--signal lfsr_ena_write		: std_logic;

begin

--  Input : CONFIG REGISTER FORMAT 
-- config_register = {   EMR(Enable/Disable DLL),
--                       BMR (Normal operation/Normal Operation with Reset DLL),
--                       BMR/EMR,
--                       CAS_latency (3),
--                       Burst type ,
--                       Burst_length (3) }
--
-- Input : COMMAND REGISTER FORMAT
--          000  - NOP
--          001  - Precharge 
--          010  - Auto Refresh
--          011  - SElf REfresh
--          100  - Write Request
--          101  - Load Mode Register
--          110  - Read request
--          111  - Burst terminate
--
-- Input : Address format
--   row address = input address(19 downto 8)
--   column addrs = input address( 7 downto 0)
--
-- provide u_cmd
-- provide u_config_parms

--  Terminals assignment 
--  Input terminals

clk         <= fpga_clk;
cmd_ack     <= u_ack;
data_valid  <= u_data_val;

ctrl_ready  <= '1';

u_addr(23 downto 0) <= addr_out(23 downto 0);
u_data_i            <= lfsr_data;
u_config_parms      <= "0000110010";

process(clk)
begin
  if clk'event and clk = '1' then
    rst0_r <= fpga_rst0;
  end if;
end process;

process(clk90)
begin
  if clk90'event and clk90 = '1' then
    rst90_r <= fpga_rst90;
  end if;
end process;

process(clk)
begin
  if clk'event and clk = '0' then
    rst180_r <= fpga_rst180;
  end if;
end process; 

process(clk90)
begin
  if clk90'event and clk90 = '0' then
    rst270_r <= fpga_rst270;
  end if;
end process;


process(clk90)
begin
 if clk90'event and clk90 = '1' then
  if rst90_r = '1' then
     lfsr_ena <= '0';
  else
     if ((r_w = '1') and (u_data_val = '1')) then
         lfsr_ena <= '1';
     elsif ((r_w = '0') and (u_ack = '1')) then
         lfsr_ena <= '1';
     else
         lfsr_ena <= '0';
     end if;
  end if;
 end if;
end process;





INST1 : addr_gen port map ( clk            => clk,
                            rst            => rst0_r,
                            addr_rst       => addr_rst,
                            addr_inc       => addr_inc,
                            addr_out       => addr_out,
                            column_address => column_address_count,
                            test_cnt_ena   => ctrl_ready,
                            test_out       => test_cnt,
                            burst_done     => burst_done,
                            cnt_roll       => cnt_roll);

INST_2 : cmd_fsm port map ( 
                            clk          => clk,
                            clk90        => clk90,
                            cmd_ack      => cmd_ack,
                            cnt_roll     => cnt_roll,
                            dip2         => dip2,
                            dly_tc       => dly_tc,
                            r_w          => r_w,
                            refresh_done => ar_done,
                            rst          => rst0_r,
                            rst90        => rst90_r,
                            rst180       => rst180_r,
                            init_val     => init_done,
                            u_data_val   => u_data_val,
                            addr_inc     => addr_inc,
                            addr_rst     => addr_rst,
                            u_cmd        => u_cmd,
                            dly_inc      => dly_inc,
                            init_counter => state,
                            lfsr_rst     => lfsr_rst);
                           

INST3 : cmp_data 
                  port map ( clk            => clk90,
                            data_valid     => data_valid,
                            lfsr_data      => lfsr_data,
                            read_data      => u_data_o,
                            rst            => rst90_r,
                            led_error_output => led_error_output,
                            data_valid_out => data_valid_out
                            );

INST5 : lfsr32 
                port map ( clk      => clk90,
                          rst      => rst90_r,
                          lfsr_rst => lfsr_rst,
                          lfsr_ena => lfsr_ena,
                          lfsr_out => lfsr_data);

INST6 : r_w_dly port map ( clk     => clk,
                           rst     => rst180_r,
                           dly_inc => dly_inc,
                           dly_tc  => dly_tc,
                           r_w     => r_w);

end arc_ddr1_test_bench;