lfsr32.vhd

xinlinx s vhdl code model and user guider

library ieee;
use ieee.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity lfsr32 is
  port (
        clk      : in std_logic;
        rst      : in std_logic;
        lfsr_rst : in std_logic;
        lfsr_ena : in std_logic;
        lfsr_out : out std_logic_vector(143 downto 0));
end lfsr32;

architecture arc_lfsr32 of lfsr32 is

signal lfsr : std_logic_vector(15  downto 0);
signal counter_r : std_logic_vector(7  downto 0);
signal counter_f : std_logic_vector(7  downto 0);
signal counter   : std_logic_vector(15  downto 0);

begin

counter_r <= "00000000" when ((rst = '1') or (lfsr_rst = '1')) else
             (lfsr(15 downto 8) + 1) when (lfsr_ena = '1') else
             lfsr(15 downto 8);
             
counter_f <= "00000000" when ((rst = '1') or (lfsr_rst = '1')) else
             (lfsr(15 downto 8) + 1) when (lfsr_ena = '1') else
             lfsr(15 downto 8); 
             
counter  <= counter_r & counter_f;                          
           

process(clk)
begin
 if rising_edge(clk) then	
  if (rst = '1') then
   lfsr <= (others => '0');
  else
   if lfsr_rst = '1' then
     lfsr <= (others => '0');
   elsif lfsr_ena = '1' then
--     lfsr <= ((lfsr(15) xnor lfsr(14) xnor lfsr(12) xnor lfsr(3)) & lfsr(15 downto 1));
     lfsr <= counter;
   else
     lfsr <= lfsr;
   end if;
  end if;
 end if;
end process;	

lfsr_out <= lfsr & lfsr & lfsr & lfsr & lfsr & lfsr & lfsr & lfsr & lfsr;

end arc_lfsr32;