cmp_data.vhd

xinlinx s vhdl code model and user guider

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
--
-- pragma translate_off
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
-- pragma translate_on

entity cmp_data is
port(
     clk            : in std_logic;
     data_valid     : in std_logic;
     lfsr_data      : in std_logic_vector(143 downto 0);
     read_data      : in std_logic_vector(143 downto 0);
     rst            : in std_logic;
     led_error_output : out std_logic;
     data_valid_out : out std_logic
     );
end cmp_data;

architecture arc_cmp_data of cmp_data is

component OBUF 
	port(
	     O    :	out   STD_LOGIC;
	     I    :	in    STD_LOGIC
	     );
	end component;

type state is (idle, flag_error);
signal led_state     : state;
signal valid         : std_logic;
signal error         : std_logic;
signal lfsr_0        : std_logic_vector(71 downto 0);
signal lfsr_1        : std_logic_vector(71 downto 0);
signal data_0        : std_logic_vector(71 downto 0);
signal data_1        : std_logic_vector(71 downto 0);
signal byte_err      : std_logic_vector(1 downto 0);
signal valid_1       : std_logic;
signal read_data_reg : std_logic_vector(143 downto 0);

begin

process(clk)
begin
 if clk'event and clk = '1' then
  if rst = '1' then
    read_data_reg <= (others => '0');
  else
    read_data_reg <= read_data;
  end if;
 end if;
end process;

process (clk)
begin
 if clk'event and clk ='1' then
  if rst = '1' then
      valid_1 <= '0';
      valid <= '0';
  else
      valid_1 <= data_valid;
      valid <= data_valid;
  end if;
 end if;
end process;       

data_valid_out <= valid;


data_0 <= read_data_reg(71 downto 0);
data_1 <= read_data_reg(143 downto 72);
			
lfsr_0 <= lfsr_data( 71 downto 0 );
lfsr_1 <= lfsr_data(143 downto 72 );

process(clk)
begin
	if clk'event and clk = '1' then
		if (rst='1') then
                        byte_err <= "00";
		else
                        if (valid = '1') then
				if (data_0(71 downto 0) /= lfsr_0(71 downto 0)) then
					byte_err(0) <= '1';
				else
					byte_err(0) <= '0';
				end if;

				if (data_1(71 downto 0) /= lfsr_1(71 downto 0)) then
					byte_err(1) <= '1';
				else
					byte_err(1) <= '0';
				end if;
			else
				byte_err <= (others => '0');
			end if;
		end if;
	end if;
end process;
error <= byte_err(0) or byte_err(1);
-- LED error output
process(clk)
begin
   if clk'event and clk = '1' then
      if rst = '1' then
          led_state <= idle;
      else
         case led_state is
            when idle =>
                if error = '1' then
                     led_state <= flag_error;
                else
                     led_state <= idle;
                end if;
            when flag_error =>
                led_state <= flag_error;
         end case;
      end if;
  end if;
end process;

led_error_output <= '1' when led_state = flag_error else
                    '0';
              
	
end arc_cmp_data;