ft_top.tan.rpt

用quartus6原理编辑方式写的简易频率计我自己的实验来的 保证能使请您认真查看谢谢

            Info: 12: + IC(0.000 ns) + CELL(7.000 ns) = 97.000 ns; Loc. = LC8; Fanout = 5; REG Node = 'conter8:13|74390:1|33'
            Info: 13: + IC(2.000 ns) + CELL(6.000 ns) = 105.000 ns; Loc. = LC16; Fanout = 4; REG Node = 'conter8:13|74390:1|32'
            Info: Total cell delay = 89.000 ns ( 84.76 % )
            Info: Total interconnect delay = 16.000 ns ( 15.24 % )
    Info: + Micro clock to output delay of source is 1.000 ns
    Info: + Micro setup delay of destination is 4.000 ns
Warning: Circuit may not operate. Detected 8 non-operational path(s) clocked by clock "CLK" with clock skew larger than data delay. See Compilation Report for details.
Info: Found hold time violation between source  pin or register "conter8:13|74390:1|32" and destination pin or register "conter8:13|74390:1|32" for clock "CLK" (Hold time is 39.0 ns)
    Info: + Largest clock skew is 44.000 ns
        Info: + Longest clock path from clock "CLK" to destination register is 116.000 ns
            Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 1; CLK Node = 'CLK'
            Info: 2: + IC(0.000 ns) + CELL(1.000 ns) = 4.000 ns; Loc. = LC28; Fanout = 10; REG Node = 'tf_ctro:18|7493:2|16'
            Info: 3: + IC(2.000 ns) + CELL(7.000 ns) = 13.000 ns; Loc. = LC22; Fanout = 8; REG Node = 'tf_ctro:18|7493:2|13'
            Info: 4: + IC(2.000 ns) + CELL(8.000 ns) = 23.000 ns; Loc. = SEXP17; Fanout = 1; COMB Node = 'conter8:13|10~7'
            Info: 5: + IC(0.000 ns) + CELL(7.000 ns) = 30.000 ns; Loc. = LC30; Fanout = 6; REG Node = 'conter8:13|74390:1|7'
            Info: 6: + IC(2.000 ns) + CELL(7.000 ns) = 39.000 ns; Loc. = LC7; Fanout = 5; REG Node = 'conter8:13|74390:1|3'
            Info: 7: + IC(2.000 ns) + CELL(8.000 ns) = 49.000 ns; Loc. = SEXP2; Fanout = 1; COMB Node = 'conter8:13|74390:1|20~7'
            Info: 8: + IC(0.000 ns) + CELL(7.000 ns) = 56.000 ns; Loc. = LC13; Fanout = 6; REG Node = 'conter8:13|74390:1|6'
            Info: 9: + IC(2.000 ns) + CELL(7.000 ns) = 65.000 ns; Loc. = LC11; Fanout = 5; REG Node = 'conter8:13|74390:1|5'
            Info: 10: + IC(2.000 ns) + CELL(8.000 ns) = 75.000 ns; Loc. = SEXP3; Fanout = 1; COMB Node = 'conter8:13|0~9'
            Info: 11: + IC(0.000 ns) + CELL(7.000 ns) = 82.000 ns; Loc. = LC1; Fanout = 5; REG Node = 'conter8:13|74390:1|34'
            Info: 12: + IC(2.000 ns) + CELL(7.000 ns) = 91.000 ns; Loc. = LC2; Fanout = 4; REG Node = 'conter8:13|74390:1|31'
            Info: 13: + IC(2.000 ns) + CELL(8.000 ns) = 101.000 ns; Loc. = SEXP1; Fanout = 1; COMB Node = 'conter8:13|74390:1|29~7'
            Info: 14: + IC(0.000 ns) + CELL(7.000 ns) = 108.000 ns; Loc. = LC8; Fanout = 5; REG Node = 'conter8:13|74390:1|33'
            Info: 15: + IC(2.000 ns) + CELL(6.000 ns) = 116.000 ns; Loc. = LC16; Fanout = 4; REG Node = 'conter8:13|74390:1|32'
            Info: Total cell delay = 98.000 ns ( 84.48 % )
            Info: Total interconnect delay = 18.000 ns ( 15.52 % )
        Info: - Shortest clock path from clock "CLK" to source register is 72.000 ns
            Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 1; CLK Node = 'CLK'
            Info: 2: + IC(0.000 ns) + CELL(1.000 ns) = 4.000 ns; Loc. = LC28; Fanout = 10; REG Node = 'tf_ctro:18|7493:2|16'
            Info: 3: + IC(2.000 ns) + CELL(7.000 ns) = 13.000 ns; Loc. = LC22; Fanout = 8; REG Node = 'tf_ctro:18|7493:2|13'
            Info: 4: + IC(2.000 ns) + CELL(8.000 ns) = 23.000 ns; Loc. = SEXP17; Fanout = 1; COMB Node = 'conter8:13|10~7'
            Info: 5: + IC(0.000 ns) + CELL(7.000 ns) = 30.000 ns; Loc. = LC30; Fanout = 6; REG Node = 'conter8:13|74390:1|7'
            Info: 6: + IC(2.000 ns) + CELL(8.000 ns) = 40.000 ns; Loc. = SEXP3; Fanout = 1; COMB Node = 'conter8:13|0~9'
            Info: 7: + IC(0.000 ns) + CELL(7.000 ns) = 47.000 ns; Loc. = LC1; Fanout = 5; REG Node = 'conter8:13|74390:1|34'
            Info: 8: + IC(2.000 ns) + CELL(8.000 ns) = 57.000 ns; Loc. = SEXP1; Fanout = 1; COMB Node = 'conter8:13|74390:1|29~7'
            Info: 9: + IC(0.000 ns) + CELL(7.000 ns) = 64.000 ns; Loc. = LC8; Fanout = 5; REG Node = 'conter8:13|74390:1|33'
            Info: 10: + IC(2.000 ns) + CELL(6.000 ns) = 72.000 ns; Loc. = LC16; Fanout = 4; REG Node = 'conter8:13|74390:1|32'
            Info: Total cell delay = 62.000 ns ( 86.11 % )
            Info: Total interconnect delay = 10.000 ns ( 13.89 % )
    Info: - Micro clock to output delay of source is 1.000 ns
    Info: - Shortest register to register delay is 8.000 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC16; Fanout = 4; REG Node = 'conter8:13|74390:1|32'
        Info: 2: + IC(0.000 ns) + CELL(8.000 ns) = 8.000 ns; Loc. = LC16; Fanout = 4; REG Node = 'conter8:13|74390:1|32'
        Info: Total cell delay = 8.000 ns ( 100.00 % )
    Info: + Micro hold delay of destination is 4.000 ns
Warning: Circuit may not operate. Detected 8 non-operational path(s) clocked by clock "F_IN" with clock skew larger than data delay. See Compilation Report for details.
Info: Found hold time violation between source  pin or register "conter8:13|74390:1|32" and destination pin or register "conter8:13|74390:1|32" for clock "F_IN" (Hold time is 39.0 ns)
    Info: + Largest clock skew is 44.000 ns
        Info: + Longest clock path from clock "F_IN" to destination register is 105.000 ns
            Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_52; Fanout = 1; CLK Node = 'F_IN'
            Info: 2: + IC(2.000 ns) + CELL(8.000 ns) = 12.000 ns; Loc. = SEXP17; Fanout = 1; COMB Node = 'conter8:13|10~7'
            Info: 3: + IC(0.000 ns) + CELL(7.000 ns) = 19.000 ns; Loc. = LC30; Fanout = 6; REG Node = 'conter8:13|74390:1|7'
            Info: 4: + IC(2.000 ns) + CELL(7.000 ns) = 28.000 ns; Loc. = LC7; Fanout = 5; REG Node = 'conter8:13|74390:1|3'
            Info: 5: + IC(2.000 ns) + CELL(8.000 ns) = 38.000 ns; Loc. = SEXP2; Fanout = 1; COMB Node = 'conter8:13|74390:1|20~7'
            Info: 6: + IC(0.000 ns) + CELL(7.000 ns) = 45.000 ns; Loc. = LC13; Fanout = 6; REG Node = 'conter8:13|74390:1|6'
            Info: 7: + IC(2.000 ns) + CELL(7.000 ns) = 54.000 ns; Loc. = LC11; Fanout = 5; REG Node = 'conter8:13|74390:1|5'
            Info: 8: + IC(2.000 ns) + CELL(8.000 ns) = 64.000 ns; Loc. = SEXP3; Fanout = 1; COMB Node = 'conter8:13|0~9'
            Info: 9: + IC(0.000 ns) + CELL(7.000 ns) = 71.000 ns; Loc. = LC1; Fanout = 5; REG Node = 'conter8:13|74390:1|34'
            Info: 10: + IC(2.000 ns) + CELL(7.000 ns) = 80.000 ns; Loc. = LC2; Fanout = 4; REG Node = 'conter8:13|74390:1|31'
            Info: 11: + IC(2.000 ns) + CELL(8.000 ns) = 90.000 ns; Loc. = SEXP1; Fanout = 1; COMB Node = 'conter8:13|74390:1|29~7'
            Info: 12: + IC(0.000 ns) + CELL(7.000 ns) = 97.000 ns; Loc. = LC8; Fanout = 5; REG Node = 'conter8:13|74390:1|33'
            Info: 13: + IC(2.000 ns) + CELL(6.000 ns) = 105.000 ns; Loc. = LC16; Fanout = 4; REG Node = 'conter8:13|74390:1|32'
            Info: Total cell delay = 89.000 ns ( 84.76 % )
            Info: Total interconnect delay = 16.000 ns ( 15.24 % )
        Info: - Shortest clock path from clock "F_IN" to source register is 61.000 ns
            Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_52; Fanout = 1; CLK Node = 'F_IN'
            Info: 2: + IC(2.000 ns) + CELL(8.000 ns) = 12.000 ns; Loc. = SEXP17; Fanout = 1; COMB Node = 'conter8:13|10~7'
            Info: 3: + IC(0.000 ns) + CELL(7.000 ns) = 19.000 ns; Loc. = LC30; Fanout = 6; REG Node = 'conter8:13|74390:1|7'
            Info: 4: + IC(2.000 ns) + CELL(8.000 ns) = 29.000 ns; Loc. = SEXP3; Fanout = 1; COMB Node = 'conter8:13|0~9'
            Info: 5: + IC(0.000 ns) + CELL(7.000 ns) = 36.000 ns; Loc. = LC1; Fanout = 5; REG Node = 'conter8:13|74390:1|34'
            Info: 6: + IC(2.000 ns) + CELL(8.000 ns) = 46.000 ns; Loc. = SEXP1; Fanout = 1; COMB Node = 'conter8:13|74390:1|29~7'
            Info: 7: + IC(0.000 ns) + CELL(7.000 ns) = 53.000 ns; Loc. = LC8; Fanout = 5; REG Node = 'conter8:13|74390:1|33'
            Info: 8: + IC(2.000 ns) + CELL(6.000 ns) = 61.000 ns; Loc. = LC16; Fanout = 4; REG Node = 'conter8:13|74390:1|32'
            Info: Total cell delay = 53.000 ns ( 86.89 % )
            Info: Total interconnect delay = 8.000 ns ( 13.11 % )
    Info: - Micro clock to output delay of source is 1.000 ns
    Info: - Shortest register to register delay is 8.000 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC16; Fanout = 4; REG Node = 'conter8:13|74390:1|32'
        Info: 2: + IC(0.000 ns) + CELL(8.000 ns) = 8.000 ns; Loc. = LC16; Fanout = 4; REG Node = 'conter8:13|74390:1|32'
        Info: Total cell delay = 8.000 ns ( 100.00 % )
    Info: + Micro hold delay of destination is 4.000 ns
Info: tco from clock "CLK" to destination pin "COUT" through register "conter8:13|74390:1|32" is 130.000 ns
    Info: + Longest clock path from clock "CLK" to source register is 116.000 ns
        Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 1; CLK Node = 'CLK'
        Info: 2: + IC(0.000 ns) + CELL(1.000 ns) = 4.000 ns; Loc. = LC28; Fanout = 10; REG Node = 'tf_ctro:18|7493:2|16'
        Info: 3: + IC(2.000 ns) + CELL(7.000 ns) = 13.000 ns; Loc. = LC22; Fanout = 8; REG Node = 'tf_ctro:18|7493:2|13'
        Info: 4: + IC(2.000 ns) + CELL(8.000 ns) = 23.000 ns; Loc. = SEXP17; Fanout = 1; COMB Node = 'conter8:13|10~7'
        Info: 5: + IC(0.000 ns) + CELL(7.000 ns) = 30.000 ns; Loc. = LC30; Fanout = 6; REG Node = 'conter8:13|74390:1|7'
        Info: 6: + IC(2.000 ns) + CELL(7.000 ns) = 39.000 ns; Loc. = LC7; Fanout = 5; REG Node = 'conter8:13|74390:1|3'
        Info: 7: + IC(2.000 ns) + CELL(8.000 ns) = 49.000 ns; Loc. = SEXP2; Fanout = 1; COMB Node = 'conter8:13|74390:1|20~7'
        Info: 8: + IC(0.000 ns) + CELL(7.000 ns) = 56.000 ns; Loc. = LC13; Fanout = 6; REG Node = 'conter8:13|74390:1|6'
        Info: 9: + IC(2.000 ns) + CELL(7.000 ns) = 65.000 ns; Loc. = LC11; Fanout = 5; REG Node = 'conter8:13|74390:1|5'
        Info: 10: + IC(2.000 ns) + CELL(8.000 ns) = 75.000 ns; Loc. = SEXP3; Fanout = 1; COMB Node = 'conter8:13|0~9'
        Info: 11: + IC(0.000 ns) + CELL(7.000 ns) = 82.000 ns; Loc. = LC1; Fanout = 5; REG Node = 'conter8:13|74390:1|34'
        Info: 12: + IC(2.000 ns) + CELL(7.000 ns) = 91.000 ns; Loc. = LC2; Fanout = 4; REG Node = 'conter8:13|74390:1|31'
        Info: 13: + IC(2.000 ns) + CELL(8.000 ns) = 101.000 ns; Loc. = SEXP1; Fanout = 1; COMB Node = 'conter8:13|74390:1|29~7'
        Info: 14: + IC(0.000 ns) + CELL(7.000 ns) = 108.000 ns; Loc. = LC8; Fanout = 5; REG Node = 'conter8:13|74390:1|33'
        Info: 15: + IC(2.000 ns) + CELL(6.000 ns) = 116.000 ns; Loc. = LC16; Fanout = 4; REG Node = 'conter8:13|74390:1|32'
        Info: Total cell delay = 98.000 ns ( 84.48 % )
        Info: Total interconnect delay = 18.000 ns ( 15.52 % )
    Info: + Micro clock to output delay of source is 1.000 ns
    Info: + Longest register to pin delay is 13.000 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC16; Fanout = 4; REG Node = 'conter8:13|74390:1|32'
        Info: 2: + IC(2.000 ns) + CELL(7.000 ns) = 9.000 ns; Loc. = LC3; Fanout = 1; COMB Node = 'conter8:13|19~10'
        Info: 3: + IC(0.000 ns) + CELL(4.000 ns) = 13.000 ns; Loc. = PIN_12; Fanout = 0; PIN Node = 'COUT'
        Info: Total cell delay = 11.000 ns ( 84.62 % )
        Info: Total interconnect delay = 2.000 ns ( 15.38 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 4 warnings
    Info: Processing ended: Tue May 15 22:04:11 2007
    Info: Elapsed time: 00:00:01