ft_top.tan.rpt

用quartus6原理编辑方式写的简易频率计我自己的实验来的 保证能使请您认真查看谢谢

; N/A   ; None         ; 44.000 ns  ; 74374:4|14            ; L[6] ; CLK        ;
; N/A   ; None         ; 44.000 ns  ; 74374:4|15            ; L[6] ; CLK        ;
; N/A   ; None         ; 44.000 ns  ; 74374:4|16            ; L[6] ; CLK        ;
; N/A   ; None         ; 44.000 ns  ; 74374:4|13            ; L[1] ; CLK        ;
; N/A   ; None         ; 44.000 ns  ; 74374:4|14            ; L[1] ; CLK        ;
; N/A   ; None         ; 44.000 ns  ; 74374:4|15            ; L[1] ; CLK        ;
; N/A   ; None         ; 44.000 ns  ; 74374:4|16            ; L[1] ; CLK        ;
; N/A   ; None         ; 44.000 ns  ; 74374:4|13            ; L[2] ; CLK        ;
; N/A   ; None         ; 44.000 ns  ; 74374:4|14            ; L[2] ; CLK        ;
; N/A   ; None         ; 44.000 ns  ; 74374:4|15            ; L[2] ; CLK        ;
; N/A   ; None         ; 44.000 ns  ; 74374:4|16            ; L[2] ; CLK        ;
; N/A   ; None         ; 44.000 ns  ; 74374:4|13            ; L[4] ; CLK        ;
; N/A   ; None         ; 44.000 ns  ; 74374:4|14            ; L[4] ; CLK        ;
; N/A   ; None         ; 44.000 ns  ; 74374:4|15            ; L[4] ; CLK        ;
; N/A   ; None         ; 43.000 ns  ; conter8:13|74390:1|7  ; COUT ; CLK        ;
; N/A   ; None         ; 41.000 ns  ; conter8:13|74390:1|3  ; COUT ; F_IN       ;
; N/A   ; None         ; 32.000 ns  ; conter8:13|74390:1|7  ; COUT ; F_IN       ;
+-------+--------------+------------+-----------------------+------+------------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 5.0 Build 148 04/26/2005 SJ Full Version
    Info: Processing started: Tue May 15 22:04:11 2007
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off ft_top -c ft_top
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Info: Found combinational loop of 1 nodes
    Info: Node "tf_ctro:18|16~70"
Info: Found combinational loop of 1 nodes
    Info: Node "tf_ctro:18|7~68"
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "CLK" is an undefined clock
    Info: Assuming node "F_IN" is an undefined clock
Warning: Found 16 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew
    Info: Detected ripple clock "conter8:13|74390:1|31" as buffer
    Info: Detected gated clock "conter8:13|10~7" as buffer
    Info: Detected ripple clock "conter8:13|74390:1|7" as buffer
    Info: Detected gated clock "conter8:13|74390:1|20~7" as buffer
    Info: Detected ripple clock "conter8:13|74390:1|6" as buffer
    Info: Detected ripple clock "conter8:13|74390:1|5" as buffer
    Info: Detected ripple clock "conter8:13|74390:1|3" as buffer
    Info: Detected gated clock "conter8:13|0~9" as buffer
    Info: Detected ripple clock "conter8:13|74390:1|34" as buffer
    Info: Detected gated clock "conter8:13|74390:1|29~7" as buffer
    Info: Detected ripple clock "conter8:13|74390:1|33" as buffer
    Info: Detected gated clock "tf_ctro:18|7~68" as buffer
    Info: Detected ripple clock "tf_ctro:18|7493:2|13" as buffer
    Info: Detected ripple clock "tf_ctro:18|7493:2|14" as buffer
    Info: Detected ripple clock "tf_ctro:18|7493:2|15" as buffer
    Info: Detected ripple clock "tf_ctro:18|7493:2|16" as buffer
Info: Clock "CLK" has Internal fmax of 9.26 MHz between source register "conter8:13|74390:1|32" and destination register "74374:4|19" (period= 108.0 ns)
    Info: + Longest register to register delay is 8.000 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC16; Fanout = 4; REG Node = 'conter8:13|74390:1|32'
        Info: 2: + IC(2.000 ns) + CELL(6.000 ns) = 8.000 ns; Loc. = LC15; Fanout = 17; REG Node = '74374:4|19'
        Info: Total cell delay = 6.000 ns ( 75.00 % )
        Info: Total interconnect delay = 2.000 ns ( 25.00 % )
    Info: - Smallest clock skew is -95.000 ns
        Info: + Shortest clock path from clock "CLK" to destination register is 21.000 ns
            Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 1; CLK Node = 'CLK'
            Info: 2: + IC(0.000 ns) + CELL(1.000 ns) = 4.000 ns; Loc. = LC28; Fanout = 10; REG Node = 'tf_ctro:18|7493:2|16'
            Info: 3: + IC(0.000 ns) + CELL(9.000 ns) = 13.000 ns; Loc. = LC20; Fanout = 12; COMB LOOP Node = 'tf_ctro:18|7~68'
                Info: Loc. = LC20; Node "tf_ctro:18|7~68"
            Info: 4: + IC(2.000 ns) + CELL(6.000 ns) = 21.000 ns; Loc. = LC15; Fanout = 17; REG Node = '74374:4|19'
            Info: Total cell delay = 19.000 ns ( 90.48 % )
            Info: Total interconnect delay = 2.000 ns ( 9.52 % )
        Info: - Longest clock path from clock "CLK" to source register is 116.000 ns
            Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 1; CLK Node = 'CLK'
            Info: 2: + IC(0.000 ns) + CELL(1.000 ns) = 4.000 ns; Loc. = LC28; Fanout = 10; REG Node = 'tf_ctro:18|7493:2|16'
            Info: 3: + IC(2.000 ns) + CELL(7.000 ns) = 13.000 ns; Loc. = LC22; Fanout = 8; REG Node = 'tf_ctro:18|7493:2|13'
            Info: 4: + IC(2.000 ns) + CELL(8.000 ns) = 23.000 ns; Loc. = SEXP17; Fanout = 1; COMB Node = 'conter8:13|10~7'
            Info: 5: + IC(0.000 ns) + CELL(7.000 ns) = 30.000 ns; Loc. = LC30; Fanout = 6; REG Node = 'conter8:13|74390:1|7'
            Info: 6: + IC(2.000 ns) + CELL(7.000 ns) = 39.000 ns; Loc. = LC7; Fanout = 5; REG Node = 'conter8:13|74390:1|3'
            Info: 7: + IC(2.000 ns) + CELL(8.000 ns) = 49.000 ns; Loc. = SEXP2; Fanout = 1; COMB Node = 'conter8:13|74390:1|20~7'
            Info: 8: + IC(0.000 ns) + CELL(7.000 ns) = 56.000 ns; Loc. = LC13; Fanout = 6; REG Node = 'conter8:13|74390:1|6'
            Info: 9: + IC(2.000 ns) + CELL(7.000 ns) = 65.000 ns; Loc. = LC11; Fanout = 5; REG Node = 'conter8:13|74390:1|5'
            Info: 10: + IC(2.000 ns) + CELL(8.000 ns) = 75.000 ns; Loc. = SEXP3; Fanout = 1; COMB Node = 'conter8:13|0~9'
            Info: 11: + IC(0.000 ns) + CELL(7.000 ns) = 82.000 ns; Loc. = LC1; Fanout = 5; REG Node = 'conter8:13|74390:1|34'
            Info: 12: + IC(2.000 ns) + CELL(7.000 ns) = 91.000 ns; Loc. = LC2; Fanout = 4; REG Node = 'conter8:13|74390:1|31'
            Info: 13: + IC(2.000 ns) + CELL(8.000 ns) = 101.000 ns; Loc. = SEXP1; Fanout = 1; COMB Node = 'conter8:13|74390:1|29~7'
            Info: 14: + IC(0.000 ns) + CELL(7.000 ns) = 108.000 ns; Loc. = LC8; Fanout = 5; REG Node = 'conter8:13|74390:1|33'
            Info: 15: + IC(2.000 ns) + CELL(6.000 ns) = 116.000 ns; Loc. = LC16; Fanout = 4; REG Node = 'conter8:13|74390:1|32'
            Info: Total cell delay = 98.000 ns ( 84.48 % )
            Info: Total interconnect delay = 18.000 ns ( 15.52 % )
    Info: + Micro clock to output delay of source is 1.000 ns
    Info: + Micro setup delay of destination is 4.000 ns
Info: Clock "F_IN" has Internal fmax of 13.51 MHz between source register "conter8:13|74390:1|32" and destination register "conter8:13|74390:1|31" (period= 74.0 ns)
    Info: + Longest register to register delay is 8.000 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC16; Fanout = 4; REG Node = 'conter8:13|74390:1|32'
        Info: 2: + IC(2.000 ns) + CELL(6.000 ns) = 8.000 ns; Loc. = LC2; Fanout = 4; REG Node = 'conter8:13|74390:1|31'
        Info: Total cell delay = 6.000 ns ( 75.00 % )
        Info: Total interconnect delay = 2.000 ns ( 25.00 % )
    Info: - Smallest clock skew is -61.000 ns
        Info: + Shortest clock path from clock "F_IN" to destination register is 44.000 ns
            Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_52; Fanout = 1; CLK Node = 'F_IN'
            Info: 2: + IC(2.000 ns) + CELL(8.000 ns) = 12.000 ns; Loc. = SEXP17; Fanout = 1; COMB Node = 'conter8:13|10~7'
            Info: 3: + IC(0.000 ns) + CELL(7.000 ns) = 19.000 ns; Loc. = LC30; Fanout = 6; REG Node = 'conter8:13|74390:1|7'
            Info: 4: + IC(2.000 ns) + CELL(8.000 ns) = 29.000 ns; Loc. = SEXP3; Fanout = 1; COMB Node = 'conter8:13|0~9'
            Info: 5: + IC(0.000 ns) + CELL(7.000 ns) = 36.000 ns; Loc. = LC1; Fanout = 5; REG Node = 'conter8:13|74390:1|34'
            Info: 6: + IC(2.000 ns) + CELL(6.000 ns) = 44.000 ns; Loc. = LC2; Fanout = 4; REG Node = 'conter8:13|74390:1|31'
            Info: Total cell delay = 38.000 ns ( 86.36 % )
            Info: Total interconnect delay = 6.000 ns ( 13.64 % )
        Info: - Longest clock path from clock "F_IN" to source register is 105.000 ns
            Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_52; Fanout = 1; CLK Node = 'F_IN'
            Info: 2: + IC(2.000 ns) + CELL(8.000 ns) = 12.000 ns; Loc. = SEXP17; Fanout = 1; COMB Node = 'conter8:13|10~7'
            Info: 3: + IC(0.000 ns) + CELL(7.000 ns) = 19.000 ns; Loc. = LC30; Fanout = 6; REG Node = 'conter8:13|74390:1|7'
            Info: 4: + IC(2.000 ns) + CELL(7.000 ns) = 28.000 ns; Loc. = LC7; Fanout = 5; REG Node = 'conter8:13|74390:1|3'
            Info: 5: + IC(2.000 ns) + CELL(8.000 ns) = 38.000 ns; Loc. = SEXP2; Fanout = 1; COMB Node = 'conter8:13|74390:1|20~7'
            Info: 6: + IC(0.000 ns) + CELL(7.000 ns) = 45.000 ns; Loc. = LC13; Fanout = 6; REG Node = 'conter8:13|74390:1|6'
            Info: 7: + IC(2.000 ns) + CELL(7.000 ns) = 54.000 ns; Loc. = LC11; Fanout = 5; REG Node = 'conter8:13|74390:1|5'
            Info: 8: + IC(2.000 ns) + CELL(8.000 ns) = 64.000 ns; Loc. = SEXP3; Fanout = 1; COMB Node = 'conter8:13|0~9'
            Info: 9: + IC(0.000 ns) + CELL(7.000 ns) = 71.000 ns; Loc. = LC1; Fanout = 5; REG Node = 'conter8:13|74390:1|34'
            Info: 10: + IC(2.000 ns) + CELL(7.000 ns) = 80.000 ns; Loc. = LC2; Fanout = 4; REG Node = 'conter8:13|74390:1|31'
            Info: 11: + IC(2.000 ns) + CELL(8.000 ns) = 90.000 ns; Loc. = SEXP1; Fanout = 1; COMB Node = 'conter8:13|74390:1|29~7'