tf_ctro.tan.qmsg

用quartus6原理编辑方式写的简易频率计我自己的实验来的 保证能使请您认真查看谢谢

{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "tf_ctro.bdf" "" { Schematic "E:/ft_top/tf_ctro.bdf" { { 368 88 256 384 "clk" "" } } } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0}  } {  } 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "1 " "Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "7493:2\|16 " "Info: Detected ripple clock \"7493:2\|16\" as buffer" {  } { { "7493.bdf" "" { Schematic "c:/altera/quartus50/libraries/others/maxplus2/7493.bdf" { { 48 480 544 128 "16" "" } } } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "7493:2\|16" } } } }  } 0}  } {  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register 7493:2\|15 register 7493:2\|13 76.92 MHz 13.0 ns Internal " "Info: Clock \"clk\" has Internal fmax of 76.92 MHz between source register \"7493:2\|15\" and destination register \"7493:2\|13\" (period= 13.0 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.000 ns + Longest register register " "Info: + Longest register to register delay is 8.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns 7493:2\|15 1 REG LC2 9 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC2; Fanout = 9; REG Node = '7493:2\|15'" {  } { { "E:/ft_top/db/tf_ctro_cmp.qrpt" "" { Report "E:/ft_top/db/tf_ctro_cmp.qrpt" Compiler "tf_ctro" "UNKNOWN" "V1" "E:/ft_top/db/tf_ctro.quartus_db" { Floorplan "E:/ft_top/" "" "" { 7493:2|15 } "NODE_NAME" } "" } } { "7493.bdf" "" { Schematic "c:/altera/quartus50/libraries/others/maxplus2/7493.bdf" { { 184 480 544 264 "15" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(6.000 ns) 8.000 ns 7493:2\|13 2 REG LC3 8 " "Info: 2: + IC(2.000 ns) + CELL(6.000 ns) = 8.000 ns; Loc. = LC3; Fanout = 8; REG Node = '7493:2\|13'" {  } { { "E:/ft_top/db/tf_ctro_cmp.qrpt" "" { Report "E:/ft_top/db/tf_ctro_cmp.qrpt" Compiler "tf_ctro" "UNKNOWN" "V1" "E:/ft_top/db/tf_ctro.quartus_db" { Floorplan "E:/ft_top/" "" "8.000 ns" { 7493:2|15 7493:2|13 } "NODE_NAME" } "" } } { "7493.bdf" "" { Schematic "c:/altera/quartus50/libraries/others/maxplus2/7493.bdf" { { 456 480 544 536 "13" "" } } } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.000 ns 75.00 % " "Info: Total cell delay = 6.000 ns ( 75.00 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns 25.00 % " "Info: Total interconnect delay = 2.000 ns ( 25.00 % )" {  } {  } 0}  } { { "E:/ft_top/db/tf_ctro_cmp.qrpt" "" { Report "E:/ft_top/db/tf_ctro_cmp.qrpt" Compiler "tf_ctro" "UNKNOWN" "V1" "E:/ft_top/db/tf_ctro.quartus_db" { Floorplan "E:/ft_top/" "" "8.000 ns" { 7493:2|15 7493:2|13 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "8.000 ns" { 7493:2|15 7493:2|13 } { 0.000ns 2.000ns } { 0.000ns 6.000ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 12.000 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 12.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns clk 1 CLK PIN_83 1 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 1; CLK Node = 'clk'" {  } { { "E:/ft_top/db/tf_ctro_cmp.qrpt" "" { Report "E:/ft_top/db/tf_ctro_cmp.qrpt" Compiler "tf_ctro" "UNKNOWN" "V1" "E:/ft_top/db/tf_ctro.quartus_db" { Floorplan "E:/ft_top/" "" "" { clk } "NODE_NAME" } "" } } { "tf_ctro.bdf" "" { Schematic "E:/ft_top/tf_ctro.bdf" { { 368 88 256 384 "clk" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.000 ns) 4.000 ns 7493:2\|16 2 REG LC1 10 " "Info: 2: + IC(0.000 ns) + CELL(1.000 ns) = 4.000 ns; Loc. = LC1; Fanout = 10; REG Node = '7493:2\|16'" {  } { { "E:/ft_top/db/tf_ctro_cmp.qrpt" "" { Report "E:/ft_top/db/tf_ctro_cmp.qrpt" Compiler "tf_ctro" "UNKNOWN" "V1" "E:/ft_top/db/tf_ctro.quartus_db" { Floorplan "E:/ft_top/" "" "1.000 ns" { clk 7493:2|16 } "NODE_NAME" } "" } } { "7493.bdf" "" { Schematic "c:/altera/quartus50/libraries/others/maxplus2/7493.bdf" { { 48 480 544 128 "16" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(6.000 ns) 12.000 ns 7493:2\|13 3 REG LC3 8 " "Info: 3: + IC(2.000 ns) + CELL(6.000 ns) = 12.000 ns; Loc. = LC3; Fanout = 8; REG Node = '7493:2\|13'" {  } { { "E:/ft_top/db/tf_ctro_cmp.qrpt" "" { Report "E:/ft_top/db/tf_ctro_cmp.qrpt" Compiler "tf_ctro" "UNKNOWN" "V1" "E:/ft_top/db/tf_ctro.quartus_db" { Floorplan "E:/ft_top/" "" "8.000 ns" { 7493:2|16 7493:2|13 } "NODE_NAME" } "" } } { "7493.bdf" "" { Schematic "c:/altera/quartus50/libraries/others/maxplus2/7493.bdf" { { 456 480 544 536 "13" "" } } } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "10.000 ns 83.33 % " "Info: Total cell delay = 10.000 ns ( 83.33 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns 16.67 % " "Info: Total interconnect delay = 2.000 ns ( 16.67 % )" {  } {  } 0}  } { { "E:/ft_top/db/tf_ctro_cmp.qrpt" "" { Report "E:/ft_top/db/tf_ctro_cmp.qrpt" Compiler "tf_ctro" "UNKNOWN" "V1" "E:/ft_top/db/tf_ctro.quartus_db" { Floorplan "E:/ft_top/" "" "12.000 ns" { clk 7493:2|16 7493:2|13 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "12.000 ns" { clk clk~out 7493:2|16 7493:2|13 } { 0.000ns 0.000ns 0.000ns 2.000ns } { 0.000ns 3.000ns 1.000ns 6.000ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 12.000 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 12.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns clk 1 CLK PIN_83 1 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 1; CLK Node = 'clk'" {  } { { "E:/ft_top/db/tf_ctro_cmp.qrpt" "" { Report "E:/ft_top/db/tf_ctro_cmp.qrpt" Compiler "tf_ctro" "UNKNOWN" "V1" "E:/ft_top/db/tf_ctro.quartus_db" { Floorplan "E:/ft_top/" "" "" { clk } "NODE_NAME" } "" } } { "tf_ctro.bdf" "" { Schematic "E:/ft_top/tf_ctro.bdf" { { 368 88 256 384 "clk" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.000 ns) 4.000 ns 7493:2\|16 2 REG LC1 10 " "Info: 2: + IC(0.000 ns) + CELL(1.000 ns) = 4.000 ns; Loc. = LC1; Fanout = 10; REG Node = '7493:2\|16'" {  } { { "E:/ft_top/db/tf_ctro_cmp.qrpt" "" { Report "E:/ft_top/db/tf_ctro_cmp.qrpt" Compiler "tf_ctro" "UNKNOWN" "V1" "E:/ft_top/db/tf_ctro.quartus_db" { Floorplan "E:/ft_top/" "" "1.000 ns" { clk 7493:2|16 } "NODE_NAME" } "" } } { "7493.bdf" "" { Schematic "c:/altera/quartus50/libraries/others/maxplus2/7493.bdf" { { 48 480 544 128 "16" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(6.000 ns) 12.000 ns 7493:2\|15 3 REG LC2 9 " "Info: 3: + IC(2.000 ns) + CELL(6.000 ns) = 12.000 ns; Loc. = LC2; Fanout = 9; REG Node = '7493:2\|15'" {  } { { "E:/ft_top/db/tf_ctro_cmp.qrpt" "" { Report "E:/ft_top/db/tf_ctro_cmp.qrpt" Compiler "tf_ctro" "UNKNOWN" "V1" "E:/ft_top/db/tf_ctro.quartus_db" { Floorplan "E:/ft_top/" "" "8.000 ns" { 7493:2|16 7493:2|15 } "NODE_NAME" } "" } } { "7493.bdf" "" { Schematic "c:/altera/quartus50/libraries/others/maxplus2/7493.bdf" { { 184 480 544 264 "15" "" } } } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "10.000 ns 83.33 % " "Info: Total cell delay = 10.000 ns ( 83.33 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns 16.67 % " "Info: Total interconnect delay = 2.000 ns ( 16.67 % )" {  } {  } 0}  } { { "E:/ft_top/db/tf_ctro_cmp.qrpt" "" { Report "E:/ft_top/db/tf_ctro_cmp.qrpt" Compiler "tf_ctro" "UNKNOWN" "V1" "E:/ft_top/db/tf_ctro.quartus_db" { Floorplan "E:/ft_top/" "" "12.000 ns" { clk 7493:2|16 7493:2|15 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "12.000 ns" { clk clk~out 7493:2|16 7493:2|15 } { 0.000ns 0.000ns 0.000ns 2.000ns } { 0.000ns 3.000ns 1.000ns 6.000ns } } }  } 0}  } { { "E:/ft_top/db/tf_ctro_cmp.qrpt" "" { Report "E:/ft_top/db/tf_ctro_cmp.qrpt" Compiler "tf_ctro" "UNKNOWN" "V1" "E:/ft_top/db/tf_ctro.quartus_db" { Floorplan "E:/ft_top/" "" "12.000 ns" { clk 7493:2|16 7493:2|13 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "12.000 ns" { clk clk~out 7493:2|16 7493:2|13 } { 0.000ns 0.000ns 0.000ns 2.000ns } { 0.000ns 3.000ns 1.000ns 6.000ns } } } { "E:/ft_top/db/tf_ctro_cmp.qrpt" "" { Report "E:/ft_top/db/tf_ctro_cmp.qrpt" Compiler "tf_ctro" "UNKNOWN" "V1" "E:/ft_top/db/tf_ctro.quartus_db" { Floorplan "E:/ft_top/" "" "12.000 ns" { clk 7493:2|16 7493:2|15 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "12.000 ns" { clk clk~out 7493:2|16 7493:2|15 } { 0.000ns 0.000ns 0.000ns 2.000ns } { 0.000ns 3.000ns 1.000ns 6.000ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.000 ns + " "Info: + Micro clock to output delay of source is 1.000 ns" {  } { { "7493.bdf" "" { Schematic "c:/altera/quartus50/libraries/others/maxplus2/7493.bdf" { { 184 480 544 264 "15" "" } } } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "4.000 ns + " "Info: + Micro setup delay of destination is 4.000 ns" {  } { { "7493.bdf" "" { Schematic "c:/altera/quartus50/libraries/others/maxplus2/7493.bdf" { { 456 480 544 536 "13" "" } } } }  } 0}  } { { "E:/ft_top/db/tf_ctro_cmp.qrpt" "" { Report "E:/ft_top/db/tf_ctro_cmp.qrpt" Compiler "tf_ctro" "UNKNOWN" "V1" "E:/ft_top/db/tf_ctro.quartus_db" { Floorplan "E:/ft_top/" "" "8.000 ns" { 7493:2|15 7493:2|13 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "8.000 ns" { 7493:2|15 7493:2|13 } { 0.000ns 2.000ns } { 0.000ns 6.000ns } } } { "E:/ft_top/db/tf_ctro_cmp.qrpt" "" { Report "E:/ft_top/db/tf_ctro_cmp.qrpt" Compiler "tf_ctro" "UNKNOWN" "V1" "E:/ft_top/db/tf_ctro.quartus_db" { Floorplan "E:/ft_top/" "" "12.000 ns" { clk 7493:2|16 7493:2|13 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "12.000 ns" { clk clk~out 7493:2|16 7493:2|13 } { 0.000ns 0.000ns 0.000ns 2.000ns } { 0.000ns 3.000ns 1.000ns 6.000ns } } } { "E:/ft_top/db/tf_ctro_cmp.qrpt" "" { Report "E:/ft_top/db/tf_ctro_cmp.qrpt" Compiler "tf_ctro" "UNKNOWN" "V1" "E:/ft_top/db/tf_ctro.quartus_db" { Floorplan "E:/ft_top/" "" "12.000 ns" { clk 7493:2|16 7493:2|15 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "12.000 ns" { clk clk~out 7493:2|16 7493:2|15 } { 0.000ns 0.000ns 0.000ns 2.000ns } { 0.000ns 3.000ns 1.000ns 6.000ns } } }  } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk clr 7493:2\|15 26.000 ns register " "Info: tco from clock \"clk\" to destination pin \"clr\" through register \"7493:2\|15\" is 26.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 12.000 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 12.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns clk 1 CLK PIN_83 1 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 1; CLK Node = 'clk'" {  } { { "E:/ft_top/db/tf_ctro_cmp.qrpt" "" { Report "E:/ft_top/db/tf_ctro_cmp.qrpt" Compiler "tf_ctro" "UNKNOWN" "V1" "E:/ft_top/db/tf_ctro.quartus_db" { Floorplan "E:/ft_top/" "" "" { clk } "NODE_NAME" } "" } } { "tf_ctro.bdf" "" { Schematic "E:/ft_top/tf_ctro.bdf" { { 368 88 256 384 "clk" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.000 ns) 4.000 ns 7493:2\|16 2 REG LC1 10 " "Info: 2: + IC(0.000 ns) + CELL(1.000 ns) = 4.000 ns; Loc. = LC1; Fanout = 10; REG Node = '7493:2\|16'" {  } { { "E:/ft_top/db/tf_ctro_cmp.qrpt" "" { Report "E:/ft_top/db/tf_ctro_cmp.qrpt" Compiler "tf_ctro" "UNKNOWN" "V1" "E:/ft_top/db/tf_ctro.quartus_db" { Floorplan "E:/ft_top/" "" "1.000 ns" { clk 7493:2|16 } "NODE_NAME" } "" } } { "7493.bdf" "" { Schematic "c:/altera/quartus50/libraries/others/maxplus2/7493.bdf" { { 48 480 544 128 "16" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(6.000 ns) 12.000 ns 7493:2\|15 3 REG LC2 9 " "Info: 3: + IC(2.000 ns) + CELL(6.000 ns) = 12.000 ns; Loc. = LC2; Fanout = 9; REG Node = '7493:2\|15'" {  } { { "E:/ft_top/db/tf_ctro_cmp.qrpt" "" { Report "E:/ft_top/db/tf_ctro_cmp.qrpt" Compiler "tf_ctro" "UNKNOWN" "V1" "E:/ft_top/db/tf_ctro.quartus_db" { Floorplan "E:/ft_top/" "" "8.000 ns" { 7493:2|16 7493:2|15 } "NODE_NAME" } "" } } { "7493.bdf" "" { Schematic "c:/altera/quartus50/libraries/others/maxplus2/7493.bdf" { { 184 480 544 264 "15" "" } } } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "10.000 ns 83.33 % " "Info: Total cell delay = 10.000 ns ( 83.33 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns 16.67 % " "Info: Total interconnect delay = 2.000 ns ( 16.67 % )" {  } {  } 0}  } { { "E:/ft_top/db/tf_ctro_cmp.qrpt" "" { Report "E:/ft_top/db/tf_ctro_cmp.qrpt" Compiler "tf_ctro" "UNKNOWN" "V1" "E:/ft_top/db/tf_ctro.quartus_db" { Floorplan "E:/ft_top/" "" "12.000 ns" { clk 7493:2|16 7493:2|15 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "12.000 ns" { clk clk~out 7493:2|16 7493:2|15 } { 0.000ns 0.000ns 0.000ns 2.000ns } { 0.000ns 3.000ns 1.000ns 6.000ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.000 ns + " "Info: + Micro clock to output delay of source is 1.000 ns" {  } { { "7493.bdf" "" { Schematic "c:/altera/quartus50/libraries/others/maxplus2/7493.bdf" { { 184 480 544 264 "15" "" } } } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "13.000 ns + Longest register pin " "Info: + Longest register to pin delay is 13.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns 7493:2\|15 1 REG LC2 9 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC2; Fanout = 9; REG Node = '7493:2\|15'" {  } { { "E:/ft_top/db/tf_ctro_cmp.qrpt" "" { Report "E:/ft_top/db/tf_ctro_cmp.qrpt" Compiler "tf_ctro" "UNKNOWN" "V1" "E:/ft_top/db/tf_ctro.quartus_db" { Floorplan "E:/ft_top/" "" "" { 7493:2|15 } "NODE_NAME" } "" } } { "7493.bdf" "" { Schematic "c:/altera/quartus50/libraries/others/maxplus2/7493.bdf" { { 184 480 544 264 "15" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(9.000 ns) 9.000 ns 16~68 2 COMB LOOP LC6 5 " "Info: 2: + IC(0.000 ns) + CELL(9.000 ns) = 9.000 ns; Loc. = LC6; Fanout = 5; COMB LOOP Node = '16~68'" { { "Info" "ITDB_PART_OF_SCC" "16~68 LC6 " "Info: Loc. = LC6; Node \"16~68\"" {  } { { "E:/ft_top/db/tf_ctro_cmp.qrpt" "" { Report "E:/ft_top/db/tf_ctro_cmp.qrpt" Compiler "tf_ctro" "UNKNOWN" "V1" "E:/ft_top/db/tf_ctro.quartus_db" { Floorplan "E:/ft_top/" "" "" { 16~68 } "NODE_NAME" } "" } }  } 0}  } { { "E:/ft_top/db/tf_ctro_cmp.qrpt" "" { Report "E:/ft_top/db/tf_ctro_cmp.qrpt" Compiler "tf_ctro" "UNKNOWN" "V1" "E:/ft_top/db/tf_ctro.quartus_db" { Floorplan "E:/ft_top/" "" "" { 16~68 } "NODE_NAME" } "" } } { "tf_ctro.bdf" "" { Schematic "E:/ft_top/tf_ctro.bdf" { { 256 728 792 304 "16" "" } } } } { "E:/ft_top/db/tf_ctro_cmp.qrpt" "" { Report "E:/ft_top/db/tf_ctro_cmp.qrpt" Compiler "tf_ctro" "UNKNOWN" "V1" "E:/ft_top/db/tf_ctro.quartus_db" { Floorplan "E:/ft_top/" "" "9.000 ns" { 7493:2|15 16~68 } "NODE_NAME" } "" } } { "tf_ctro.bdf" "" { Schematic "E:/ft_top/tf_ctro.bdf" { { 256 728 792 304 "16" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.000 ns) 13.000 ns clr 3 PIN PIN_10 0 " "Info: 3: + IC(0.000 ns) + CELL(4.000 ns) = 13.000 ns; Loc. = PIN_10; Fanout = 0; PIN Node = 'clr'" {  } { { "E:/ft_top/db/tf_ctro_cmp.qrpt" "" { Report "E:/ft_top/db/tf_ctro_cmp.qrpt" Compiler "tf_ctro" "UNKNOWN" "V1" "E:/ft_top/db/tf_ctro.quartus_db" { Floorplan "E:/ft_top/" "" "4.000 ns" { 16~68 clr } "NODE_NAME" } "" } } { "tf_ctro.bdf" "" { Schematic "E:/ft_top/tf_ctro.bdf" { { 256 816 992 272 "clr" "" } } } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "13.000 ns 100.00 % " "Info: Total cell delay = 13.000 ns ( 100.00 % )" {  } {  } 0}  } { { "E:/ft_top/db/tf_ctro_cmp.qrpt" "" { Report "E:/ft_top/db/tf_ctro_cmp.qrpt" Compiler "tf_ctro" "UNKNOWN" "V1" "E:/ft_top/db/tf_ctro.quartus_db" { Floorplan "E:/ft_top/" "" "13.000 ns" { 7493:2|15 16~68 clr } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "13.000 ns" { 7493:2|15 16~68 clr } { 0.000ns 0.000ns 0.000ns } { 0.000ns 9.000ns 4.000ns } } }  } 0}  } { { "E:/ft_top/db/tf_ctro_cmp.qrpt" "" { Report "E:/ft_top/db/tf_ctro_cmp.qrpt" Compiler "tf_ctro" "UNKNOWN" "V1" "E:/ft_top/db/tf_ctro.quartus_db" { Floorplan "E:/ft_top/" "" "12.000 ns" { clk 7493:2|16 7493:2|15 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "12.000 ns" { clk clk~out 7493:2|16 7493:2|15 } { 0.000ns 0.000ns 0.000ns 2.000ns } { 0.000ns 3.000ns 1.000ns 6.000ns } } } { "E:/ft_top/db/tf_ctro_cmp.qrpt" "" { Report "E:/ft_top/db/tf_ctro_cmp.qrpt" Compiler "tf_ctro" "UNKNOWN" "V1" "E:/ft_top/db/tf_ctro.quartus_db" { Floorplan "E:/ft_top/" "" "13.000 ns" { 7493:2|15 16~68 clr } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "13.000 ns" { 7493:2|15 16~68 clr } { 0.000ns 0.000ns 0.000ns } { 0.000ns 9.000ns 4.000ns } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 2 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Tue May 15 18:35:20 2007 " "Info: Processing ended: Tue May 15 18:35:20 2007" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0}  } {  } 0}