tf_ctro.map.qmsg

用quartus6原理编辑方式写的简易频率计我自己的实验来的 保证能使请您认真查看谢谢

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 148 04/26/2005 SJ Full Version " "Info: Version 5.0 Build 148 04/26/2005 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Tue May 15 18:35:15 2007 " "Info: Processing started: Tue May 15 18:35:15 2007" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off tf_ctro -c tf_ctro " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off tf_ctro -c tf_ctro" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "tf_ctro.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file tf_ctro.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 tf_ctro " "Info: Found entity 1: tf_ctro" {  } { { "tf_ctro.bdf" "" { Schematic "E:/ft_top/tf_ctro.bdf" { } } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "tf_ctro " "Info: Elaborating entity \"tf_ctro\" for the top level hierarchy" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/quartus50/libraries/others/maxplus2/7493.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus50/libraries/others/maxplus2/7493.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 7493 " "Info: Found entity 1: 7493" {  } { { "7493.bdf" "" { Schematic "c:/altera/quartus50/libraries/others/maxplus2/7493.bdf" { } } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "7493 7493:2 " "Info: Elaborating entity \"7493\" for hierarchy \"7493:2\"" {  } { { "tf_ctro.bdf" "2" { Schematic "E:/ft_top/tf_ctro.bdf" { { 144 152 272 256 "2" "" } } } }  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/quartus50/libraries/others/maxplus2/74154.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus50/libraries/others/maxplus2/74154.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 74154 " "Info: Found entity 1: 74154" {  } { { "74154.bdf" "" { Schematic "c:/altera/quartus50/libraries/others/maxplus2/74154.bdf" { } } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "74154 74154:14 " "Info: Elaborating entity \"74154\" for hierarchy \"74154:14\"" {  } { { "tf_ctro.bdf" "14" { Schematic "E:/ft_top/tf_ctro.bdf" { { 96 432 552 384 "14" "" } } } }  } 0}
{ "Info" "IMTM_MTM_PROMOTE_GLOBAL" "" "Info: Promoted pin-driven signal(s) to global signal" { { "Info" "IMTM_MTM_PROMOTE_GLOBAL_CLOCK" "clk " "Info: Promoted clock signal driven by pin \"clk\" to global clock signal" {  } {  } 0}  } {  } 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "10 " "Info: Implemented 10 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "1 " "Info: Implemented 1 input pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_OPINS" "3 " "Info: Implemented 3 output pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_MCELLS" "6 " "Info: Implemented 6 macrocells" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 0 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Tue May 15 18:35:16 2007 " "Info: Processing ended: Tue May 15 18:35:16 2007" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0}  } {  } 0}