conter8.map.eqn

用quartus6原理编辑方式写的简易频率计我自己的实验来的 保证能使请您认真查看谢谢

-- Copyright (C) 1991-2005 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files any of the foregoing 
-- (including device programming or simulation files), and any 
-- associated documentation or information are expressly subject 
-- to the terms and conditions of the Altera Program License 
-- Subscription Agreement, Altera MegaCore Function License 
-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
-- Altera or its authorized distributors.  Please refer to the 
-- applicable agreement for further details.
--B1_32 is 74390:1|32
B1_32_reg_input = VCC;
B1_32 = TFFE(B1_32_reg_input, !B1_33, !clr, , );


--B1_7 is 74390:1|7
B1_7_reg_input = VCC;
B1_7 = TFFE(B1_7_reg_input, A1L2, !clr, , );


--A1L2 is 10~7
A1L2 = EXP(enb & clk);


--B1_6 is 74390:1|6
B1_6_reg_input = VCC;
B1_6 = TFFE(B1_6_reg_input, B1L5, !clr, , );


--B1L5 is 74390:1|20~7
B1L5 = EXP(!B1_3 & B1_7);


--B1_5 is 74390:1|5
B1_5_reg_input = VCC;
B1_5 = TFFE(B1_5_reg_input, !B1_6, !clr, , );


--B1_3 is 74390:1|3
B1_3_p1_out = !B1_3 & B1_5 & B1_6;
B1_3_or_out = B1_3_p1_out;
B1_3_reg_input = B1_3_or_out;
B1_3 = DFFE(B1_3_reg_input, !B1_7, !clr, , );


--B1_34 is 74390:1|34
B1_34_reg_input = VCC;
B1_34 = TFFE(B1_34_reg_input, A1L1, !clr, , );


--A1L1 is 0~9
A1L1 = EXP(B1_3 & !B1_5 & !B1_6 & B1_7);


--B1_31 is 74390:1|31
B1_31_p1_out = B1_33 & !B1_31 & B1_32;
B1_31_or_out = B1_31_p1_out;
B1_31_reg_input = B1_31_or_out;
B1_31 = DFFE(B1_31_reg_input, !B1_34, !clr, , );


--B1_33 is 74390:1|33
B1_33_reg_input = VCC;
B1_33 = TFFE(B1_33_reg_input, B1L6, !clr, , );


--B1L6 is 74390:1|29~7
B1L6 = EXP(B1_34 & !B1_31);


--A1L3 is 19~10
A1L3_p1_out = B1_34 & !B1_33 & B1_31 & !B1_32 & B1_3 & !B1_5 & !B1_6 & B1_7;
A1L3_or_out = A1L3_p1_out;
A1L3 = A1L3_or_out;


--clr is clr
--operation mode is input

clr = INPUT();


--enb is enb
--operation mode is input

enb = INPUT();


--clk is clk
--operation mode is input

clk = INPUT();


--q[6] is q[6]
--operation mode is output

q[6] = OUTPUT(B1_32);


--q[0] is q[0]
--operation mode is output

q[0] = OUTPUT(B1_7);


--q[1] is q[1]
--operation mode is output

q[1] = OUTPUT(B1_6);


--q[2] is q[2]
--operation mode is output

q[2] = OUTPUT(B1_5);


--q[3] is q[3]
--operation mode is output

q[3] = OUTPUT(B1_3);


--q[4] is q[4]
--operation mode is output

q[4] = OUTPUT(B1_34);


--q[7] is q[7]
--operation mode is output

q[7] = OUTPUT(B1_31);


--q[5] is q[5]
--operation mode is output

q[5] = OUTPUT(B1_33);


--cout is cout
--operation mode is output

cout = OUTPUT(A1L3);