conter8.tan.rpt

用quartus6原理编辑方式写的简易频率计我自己的实验来的 保证能使请您认真查看谢谢

        Info: Total cell delay = 6.000 ns ( 75.00 % )
        Info: Total interconnect delay = 2.000 ns ( 25.00 % )
    Info: - Smallest clock skew is -61.000 ns
        Info: + Shortest clock path from clock "clk" to destination register is 44.000 ns
            Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_52; Fanout = 1; CLK Node = 'clk'
            Info: 2: + IC(2.000 ns) + CELL(8.000 ns) = 12.000 ns; Loc. = SEXP17; Fanout = 1; COMB Node = '10~7'
            Info: 3: + IC(0.000 ns) + CELL(7.000 ns) = 19.000 ns; Loc. = LC17; Fanout = 6; REG Node = '74390:1|7'
            Info: 4: + IC(2.000 ns) + CELL(8.000 ns) = 29.000 ns; Loc. = SEXP5; Fanout = 1; COMB Node = '0~9'
            Info: 5: + IC(0.000 ns) + CELL(7.000 ns) = 36.000 ns; Loc. = LC13; Fanout = 5; REG Node = '74390:1|34'
            Info: 6: + IC(2.000 ns) + CELL(6.000 ns) = 44.000 ns; Loc. = LC6; Fanout = 4; REG Node = '74390:1|31'
            Info: Total cell delay = 38.000 ns ( 86.36 % )
            Info: Total interconnect delay = 6.000 ns ( 13.64 % )
        Info: - Longest clock path from clock "clk" to source register is 105.000 ns
            Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_52; Fanout = 1; CLK Node = 'clk'
            Info: 2: + IC(2.000 ns) + CELL(8.000 ns) = 12.000 ns; Loc. = SEXP17; Fanout = 1; COMB Node = '10~7'
            Info: 3: + IC(0.000 ns) + CELL(7.000 ns) = 19.000 ns; Loc. = LC17; Fanout = 6; REG Node = '74390:1|7'
            Info: 4: + IC(2.000 ns) + CELL(7.000 ns) = 28.000 ns; Loc. = LC14; Fanout = 5; REG Node = '74390:1|3'
            Info: 5: + IC(2.000 ns) + CELL(8.000 ns) = 38.000 ns; Loc. = SEXP6; Fanout = 1; COMB Node = '74390:1|20~7'
            Info: 6: + IC(0.000 ns) + CELL(7.000 ns) = 45.000 ns; Loc. = LC11; Fanout = 6; REG Node = '74390:1|6'
            Info: 7: + IC(2.000 ns) + CELL(7.000 ns) = 54.000 ns; Loc. = LC16; Fanout = 5; REG Node = '74390:1|5'
            Info: 8: + IC(2.000 ns) + CELL(8.000 ns) = 64.000 ns; Loc. = SEXP5; Fanout = 1; COMB Node = '0~9'
            Info: 9: + IC(0.000 ns) + CELL(7.000 ns) = 71.000 ns; Loc. = LC13; Fanout = 5; REG Node = '74390:1|34'
            Info: 10: + IC(2.000 ns) + CELL(7.000 ns) = 80.000 ns; Loc. = LC6; Fanout = 4; REG Node = '74390:1|31'
            Info: 11: + IC(2.000 ns) + CELL(8.000 ns) = 90.000 ns; Loc. = SEXP3; Fanout = 1; COMB Node = '74390:1|29~7'
            Info: 12: + IC(0.000 ns) + CELL(7.000 ns) = 97.000 ns; Loc. = LC5; Fanout = 5; REG Node = '74390:1|33'
            Info: 13: + IC(2.000 ns) + CELL(6.000 ns) = 105.000 ns; Loc. = LC8; Fanout = 4; REG Node = '74390:1|32'
            Info: Total cell delay = 89.000 ns ( 84.76 % )
            Info: Total interconnect delay = 16.000 ns ( 15.24 % )
    Info: + Micro clock to output delay of source is 1.000 ns
    Info: + Micro setup delay of destination is 4.000 ns
Warning: Circuit may not operate. Detected 8 non-operational path(s) clocked by clock "enb" with clock skew larger than data delay. See Compilation Report for details.
Info: Found hold time violation between source  pin or register "74390:1|32" and destination pin or register "74390:1|32" for clock "enb" (Hold time is 39.0 ns)
    Info: + Largest clock skew is 44.000 ns
        Info: + Longest clock path from clock "enb" to destination register is 105.000 ns
            Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_33; Fanout = 1; CLK Node = 'enb'
            Info: 2: + IC(2.000 ns) + CELL(8.000 ns) = 12.000 ns; Loc. = SEXP17; Fanout = 1; COMB Node = '10~7'
            Info: 3: + IC(0.000 ns) + CELL(7.000 ns) = 19.000 ns; Loc. = LC17; Fanout = 6; REG Node = '74390:1|7'
            Info: 4: + IC(2.000 ns) + CELL(7.000 ns) = 28.000 ns; Loc. = LC14; Fanout = 5; REG Node = '74390:1|3'
            Info: 5: + IC(2.000 ns) + CELL(8.000 ns) = 38.000 ns; Loc. = SEXP6; Fanout = 1; COMB Node = '74390:1|20~7'
            Info: 6: + IC(0.000 ns) + CELL(7.000 ns) = 45.000 ns; Loc. = LC11; Fanout = 6; REG Node = '74390:1|6'
            Info: 7: + IC(2.000 ns) + CELL(7.000 ns) = 54.000 ns; Loc. = LC16; Fanout = 5; REG Node = '74390:1|5'
            Info: 8: + IC(2.000 ns) + CELL(8.000 ns) = 64.000 ns; Loc. = SEXP5; Fanout = 1; COMB Node = '0~9'
            Info: 9: + IC(0.000 ns) + CELL(7.000 ns) = 71.000 ns; Loc. = LC13; Fanout = 5; REG Node = '74390:1|34'
            Info: 10: + IC(2.000 ns) + CELL(7.000 ns) = 80.000 ns; Loc. = LC6; Fanout = 4; REG Node = '74390:1|31'
            Info: 11: + IC(2.000 ns) + CELL(8.000 ns) = 90.000 ns; Loc. = SEXP3; Fanout = 1; COMB Node = '74390:1|29~7'
            Info: 12: + IC(0.000 ns) + CELL(7.000 ns) = 97.000 ns; Loc. = LC5; Fanout = 5; REG Node = '74390:1|33'
            Info: 13: + IC(2.000 ns) + CELL(6.000 ns) = 105.000 ns; Loc. = LC8; Fanout = 4; REG Node = '74390:1|32'
            Info: Total cell delay = 89.000 ns ( 84.76 % )
            Info: Total interconnect delay = 16.000 ns ( 15.24 % )
        Info: - Shortest clock path from clock "enb" to source register is 61.000 ns
            Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_33; Fanout = 1; CLK Node = 'enb'
            Info: 2: + IC(2.000 ns) + CELL(8.000 ns) = 12.000 ns; Loc. = SEXP17; Fanout = 1; COMB Node = '10~7'
            Info: 3: + IC(0.000 ns) + CELL(7.000 ns) = 19.000 ns; Loc. = LC17; Fanout = 6; REG Node = '74390:1|7'
            Info: 4: + IC(2.000 ns) + CELL(8.000 ns) = 29.000 ns; Loc. = SEXP5; Fanout = 1; COMB Node = '0~9'
            Info: 5: + IC(0.000 ns) + CELL(7.000 ns) = 36.000 ns; Loc. = LC13; Fanout = 5; REG Node = '74390:1|34'
            Info: 6: + IC(2.000 ns) + CELL(8.000 ns) = 46.000 ns; Loc. = SEXP3; Fanout = 1; COMB Node = '74390:1|29~7'
            Info: 7: + IC(0.000 ns) + CELL(7.000 ns) = 53.000 ns; Loc. = LC5; Fanout = 5; REG Node = '74390:1|33'
            Info: 8: + IC(2.000 ns) + CELL(6.000 ns) = 61.000 ns; Loc. = LC8; Fanout = 4; REG Node = '74390:1|32'
            Info: Total cell delay = 53.000 ns ( 86.89 % )
            Info: Total interconnect delay = 8.000 ns ( 13.11 % )
    Info: - Micro clock to output delay of source is 1.000 ns
    Info: - Shortest register to register delay is 8.000 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC8; Fanout = 4; REG Node = '74390:1|32'
        Info: 2: + IC(0.000 ns) + CELL(8.000 ns) = 8.000 ns; Loc. = LC8; Fanout = 4; REG Node = '74390:1|32'
        Info: Total cell delay = 8.000 ns ( 100.00 % )
    Info: + Micro hold delay of destination is 4.000 ns
Warning: Circuit may not operate. Detected 8 non-operational path(s) clocked by clock "clk" with clock skew larger than data delay. See Compilation Report for details.
Info: Found hold time violation between source  pin or register "74390:1|32" and destination pin or register "74390:1|32" for clock "clk" (Hold time is 39.0 ns)
    Info: + Largest clock skew is 44.000 ns
        Info: + Longest clock path from clock "clk" to destination register is 105.000 ns
            Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_52; Fanout = 1; CLK Node = 'clk'
            Info: 2: + IC(2.000 ns) + CELL(8.000 ns) = 12.000 ns; Loc. = SEXP17; Fanout = 1; COMB Node = '10~7'
            Info: 3: + IC(0.000 ns) + CELL(7.000 ns) = 19.000 ns; Loc. = LC17; Fanout = 6; REG Node = '74390:1|7'
            Info: 4: + IC(2.000 ns) + CELL(7.000 ns) = 28.000 ns; Loc. = LC14; Fanout = 5; REG Node = '74390:1|3'
            Info: 5: + IC(2.000 ns) + CELL(8.000 ns) = 38.000 ns; Loc. = SEXP6; Fanout = 1; COMB Node = '74390:1|20~7'
            Info: 6: + IC(0.000 ns) + CELL(7.000 ns) = 45.000 ns; Loc. = LC11; Fanout = 6; REG Node = '74390:1|6'
            Info: 7: + IC(2.000 ns) + CELL(7.000 ns) = 54.000 ns; Loc. = LC16; Fanout = 5; REG Node = '74390:1|5'
            Info: 8: + IC(2.000 ns) + CELL(8.000 ns) = 64.000 ns; Loc. = SEXP5; Fanout = 1; COMB Node = '0~9'
            Info: 9: + IC(0.000 ns) + CELL(7.000 ns) = 71.000 ns; Loc. = LC13; Fanout = 5; REG Node = '74390:1|34'
            Info: 10: + IC(2.000 ns) + CELL(7.000 ns) = 80.000 ns; Loc. = LC6; Fanout = 4; REG Node = '74390:1|31'
            Info: 11: + IC(2.000 ns) + CELL(8.000 ns) = 90.000 ns; Loc. = SEXP3; Fanout = 1; COMB Node = '74390:1|29~7'
            Info: 12: + IC(0.000 ns) + CELL(7.000 ns) = 97.000 ns; Loc. = LC5; Fanout = 5; REG Node = '74390:1|33'
            Info: 13: + IC(2.000 ns) + CELL(6.000 ns) = 105.000 ns; Loc. = LC8; Fanout = 4; REG Node = '74390:1|32'
            Info: Total cell delay = 89.000 ns ( 84.76 % )
            Info: Total interconnect delay = 16.000 ns ( 15.24 % )
        Info: - Shortest clock path from clock "clk" to source register is 61.000 ns
            Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_52; Fanout = 1; CLK Node = 'clk'
            Info: 2: + IC(2.000 ns) + CELL(8.000 ns) = 12.000 ns; Loc. = SEXP17; Fanout = 1; COMB Node = '10~7'
            Info: 3: + IC(0.000 ns) + CELL(7.000 ns) = 19.000 ns; Loc. = LC17; Fanout = 6; REG Node = '74390:1|7'
            Info: 4: + IC(2.000 ns) + CELL(8.000 ns) = 29.000 ns; Loc. = SEXP5; Fanout = 1; COMB Node = '0~9'
            Info: 5: + IC(0.000 ns) + CELL(7.000 ns) = 36.000 ns; Loc. = LC13; Fanout = 5; REG Node = '74390:1|34'
            Info: 6: + IC(2.000 ns) + CELL(8.000 ns) = 46.000 ns; Loc. = SEXP3; Fanout = 1; COMB Node = '74390:1|29~7'
            Info: 7: + IC(0.000 ns) + CELL(7.000 ns) = 53.000 ns; Loc. = LC5; Fanout = 5; REG Node = '74390:1|33'
            Info: 8: + IC(2.000 ns) + CELL(6.000 ns) = 61.000 ns; Loc. = LC8; Fanout = 4; REG Node = '74390:1|32'
            Info: Total cell delay = 53.000 ns ( 86.89 % )
            Info: Total interconnect delay = 8.000 ns ( 13.11 % )
    Info: - Micro clock to output delay of source is 1.000 ns
    Info: - Shortest register to register delay is 8.000 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC8; Fanout = 4; REG Node = '74390:1|32'
        Info: 2: + IC(0.000 ns) + CELL(8.000 ns) = 8.000 ns; Loc. = LC8; Fanout = 4; REG Node = '74390:1|32'
        Info: Total cell delay = 8.000 ns ( 100.00 % )
    Info: + Micro hold delay of destination is 4.000 ns
Info: tco from clock "clk" to destination pin "cout" through register "74390:1|32" is 119.000 ns
    Info: + Longest clock path from clock "clk" to source register is 105.000 ns
        Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_52; Fanout = 1; CLK Node = 'clk'
        Info: 2: + IC(2.000 ns) + CELL(8.000 ns) = 12.000 ns; Loc. = SEXP17; Fanout = 1; COMB Node = '10~7'
        Info: 3: + IC(0.000 ns) + CELL(7.000 ns) = 19.000 ns; Loc. = LC17; Fanout = 6; REG Node = '74390:1|7'
        Info: 4: + IC(2.000 ns) + CELL(7.000 ns) = 28.000 ns; Loc. = LC14; Fanout = 5; REG Node = '74390:1|3'
        Info: 5: + IC(2.000 ns) + CELL(8.000 ns) = 38.000 ns; Loc. = SEXP6; Fanout = 1; COMB Node = '74390:1|20~7'
        Info: 6: + IC(0.000 ns) + CELL(7.000 ns) = 45.000 ns; Loc. = LC11; Fanout = 6; REG Node = '74390:1|6'
        Info: 7: + IC(2.000 ns) + CELL(7.000 ns) = 54.000 ns; Loc. = LC16; Fanout = 5; REG Node = '74390:1|5'
        Info: 8: + IC(2.000 ns) + CELL(8.000 ns) = 64.000 ns; Loc. = SEXP5; Fanout = 1; COMB Node = '0~9'
        Info: 9: + IC(0.000 ns) + CELL(7.000 ns) = 71.000 ns; Loc. = LC13; Fanout = 5; REG Node = '74390:1|34'
        Info: 10: + IC(2.000 ns) + CELL(7.000 ns) = 80.000 ns; Loc. = LC6; Fanout = 4; REG Node = '74390:1|31'
        Info: 11: + IC(2.000 ns) + CELL(8.000 ns) = 90.000 ns; Loc. = SEXP3; Fanout = 1; COMB Node = '74390:1|29~7'
        Info: 12: + IC(0.000 ns) + CELL(7.000 ns) = 97.000 ns; Loc. = LC5; Fanout = 5; REG Node = '74390:1|33'
        Info: 13: + IC(2.000 ns) + CELL(6.000 ns) = 105.000 ns; Loc. = LC8; Fanout = 4; REG Node = '74390:1|32'
        Info: Total cell delay = 89.000 ns ( 84.76 % )
        Info: Total interconnect delay = 16.000 ns ( 15.24 % )
    Info: + Micro clock to output delay of source is 1.000 ns
    Info: + Longest register to pin delay is 13.000 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC8; Fanout = 4; REG Node = '74390:1|32'
        Info: 2: + IC(2.000 ns) + CELL(7.000 ns) = 9.000 ns; Loc. = LC3; Fanout = 1; COMB Node = '19~10'
        Info: 3: + IC(0.000 ns) + CELL(4.000 ns) = 13.000 ns; Loc. = PIN_12; Fanout = 0; PIN Node = 'cout'
        Info: Total cell delay = 11.000 ns ( 84.62 % )
        Info: Total interconnect delay = 2.000 ns ( 15.38 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 4 warnings
    Info: Processing ended: Tue May 15 11:02:07 2007
    Info: Elapsed time: 00:00:02